Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric System Lsi Design Corporation

Renesas Technology Corp.

Mitsubishi Denki Kabushiki

Mitsubishi Electric Systems Lsi Design Corporation

Michio Nakajima

Takekazu Yamashita

Akira Kitaguchi

Kiyoyuki Shiroshima

Makoto Hatakenaka

Masaaki Matsuo

Hideki Toki

Tsuyoshi Saitoh

Aki Urakami

Yukio Miyazaki

Kaoru Motonami

Nobuyuki Fujii

Tuyoshi Saitoh

In an output circuit of a semiconductor device, an output buffer circuit includes a P-channel MOS transistor and a resistor connected in series between a line of a power supply potential and an output node. Current driving capability of the output buffer circuit is adjusted by making the P-channel MOS transistor nonconductive when a fuse is not blown, and making P-channel MOS transistor conductive when the fuse is blown. Thus, desired circuit characteristics can be obtained. Further, measures against electrostatic discharge can be taken by providing the resistor between a drain of the P-channel MOS transistor and the output node.

Output circuit of semiconductor device having adjustable driving capability

A semiconductor memory device includes a plurality of regions. Each region includes memory cell arrays, an input/output circuit zone, column decoders, and a row decoder. The input/output circuit zone is placed between the memory cell arrays. The input/output circuit zone inputs or outputs data to or from the memory cell arrays selectively. As a result, high integration is realized with ease.

Semiconductor memory device having configuration suited for high integration

A read and write control circuit receives (m&times;n))-bit data output m-bit parallel from a D flip flop, and a q-bit data selection signal such that the output data from the D flip flop is written to memory circuits in units of integral multiples of (x&plus;1) bits in a total of 2 operations, in accordance with a binary value indicated by the data selection signal, where m, n, x and q indicates positive integers (x&plus;1)>m and n>2 , where m, n, x and 1 indicate positive integers and (x&plus;1)>m and n>2 . The data written to the memory circuits is read out in units of integral multiples of (x&plus;1) bits in a total of 2 operations.

Integrated circuit with efficient testing arrangement

Regarding a semiconductor device, a burn-in board can be standardized in each package. An IC (100) includes a VCC terminal (2), a GND terminal (3), input terminals (4a, 4b), and output terminals (5), and it also includes a burn-in board setting terminal (14). Input signals applied to the input terminals (4a, 4b) are transmitted to gates 16a and 16b of switching circuit (15) and processed in a function block (7). Regardless of the signals applied to the input terminals (4a, 4b), simply applying a test signal to the burn-in board setting terminal (14), a specified logic is applied to the function block (7). Only if a pin arrangement of the VCC terminal (2), the GND terminal (3), and the burn-in board setting terminal (14) is standardized and determined, burn-in can be performed indifferent of another pin arrangement of the input terminals (4a, 4b).

Semiconductor wafer and method of manufacturing the same, and

A semiconductor device test board solves a problem with conventional test boards in that test results obtained through a burn-in procedure could be identified only before the test board is taken out of a burn-in oven. Hence, conventional test boards required additional steps for checking the test results after removing the test boards from the burn-in oven. This extra step prevents the efficiency of the test from being improved. One embodiment of the present test board has indicator arms, each rotatably mounted on a pivot on the test board, for indicating, in response to a signal on a signal line, the test result of the semiconductor device associated with it. Each of the indicator arms maintains its rest position when no failure has occurred in the semiconductor device associated with it during the test. Each indicator arm changes its position if a failure has occurred in the semiconductor device during the test, and retains one of the two positions until after the test board is taken out of the burn-in oven. Thus, the test result can be determined after taking out the test board from the burn-in oven.

Semiconductor device test board and method for evaluating semiconductor

A semiconductor device capable of solving a problem of a conventional semiconductor device in that a high density integration cannot be expected because each cell, which includes a pair of N and P wells disposed adjacently, requires a countermeasure against latchup individually. The high density integration prevents an effective countermeasure against latchup. The present semiconductor device arranges two cells, which are adjacent in the direction of an alignment of the N wells and P wells, in opposite directions so that two P wells (or two N wells) of the two adjacent cells are disposed successively, and includes an isolation layer extending across the two adjacent cells to enclose the two successively disposed P wells, thereby isolating the two P wells collectively from the substrate.

Field effect transistor array including doped two-cell isolation region

A semiconductor integrated circuit includes a fuse element located on an insulating layer. The surface of the insulating layer is substantially smooth. The insulating layer is located over a capacitor. Wiring is located on the insulation layer. The fuse element and the wiring include the same material.

Semiconductor integrated circuit including a capacitor and a fuse element

A semiconductor memory device is constituted such that, when a first wiring layer provides a bit line of a first common complementary data line pair and a third wiring layer provides a bit line of a second common complementary data line pair, a second wiring layer makes an overlapped area between the bit line and the bit bar line of the second common complementary dada line pair equal to the bit line of the first common complementary data line pair and also an overlapped area between the bit line and the bit bar line of the first common complementary data line pair equal to the bit line of the second common complementary data line pair.

Semiconductor memory device having improved bit line structure

A semiconductor memory device includes memory elements, each maintaining memory contents within a period of time during which a refresh operation is repeated, and a refresh request circuit for making a refresh request. The semiconductor memory device includes refreshing circuits each of which, in response to a refresh request from the refresh request circuit, performs a refresh operation on a different number of memory elements at the same time, and a selecting circuit for selecting one refreshing circuit from among the refreshing circuits according to the number of memory elements included in the semiconductor memory device. The refresh request circuit can change the interval at which it makes a refresh request.

Semiconductor memory device and method of refreshing semiconductor

A smaller, high-speed, semiconductor memory device having redundancy is disclosed which attains an improved mass productivity. Where a main memory (20) includes a defective memory cell, a defective address designating circuit (21) stores the address of the defective memory cell. Defective address detecting circuits (22a to 22r) detect whether an address signal received at an address signal input terminal (4) coincides with an address signal from the defective address designating circuit (21). If a signal indicative of the coincidence is given to a redundancy memory circuit (23) from the defective address detecting circuits (22a to 22r), data is written in or read from defective address remedy latch circuit groups (23a to 23r) of the redundancy memory circuit (23) which correspond to the defective address detecting circuits (22a to 22r). A data selector (24) selectively outputs data received from the defective address remedy latch circuit groups (23a to 23r) or data received from the main memory (20). Thus, the redundancy memory circuit (23), which requires less space, quickly replaces the defective memory cell of the main memory (20).

Semiconductor memory device

In order to obtain a redundancy circuit which can freely arrange its fuse in a required position with disciplined accessibility after employment, a combination circuit (50) receives outputs (QA0 to QA7) obtained by decoding a column address (AXM) by a column line decoder (2), signals (QB0 to QB7) indicating a faulty line, signals (L0 to L7) generated from the signals (QB0 to QB7) and an inverted signal (ENB*), to generate signals (YS0 to YS8) for controlling selecting switches for specifying column lines. If a K-th column line is faulty, a column line selecting switch for selecting the K-th column line is forcibly turned off and an (N+1)-th column line is allocated with respect to specification of an N-th column line (N.gtoreq.K). Thus, fuse positions of redundancy circuits can be standarlized between products so that the products can be easily mass-produced and supplied at a low cost even if the redundancy circuits are contained in small quantities of various ASICs.

Redundancy circuit

A serial selection circuit is disclosed for sequentially selecting a word line in a semiconductor memory. Flipflops (latch circuits) for respectively holding the state are connected to each word line W0 to W1023. These flipflops are sequentially activated in response to two-phase non-overlap clock signals, and then deactivated. This serial selection circuit has the circuit structure being highly simplified compared with the conventional row decoder, so that the occupied area on the semiconductor chip is substantially reduced.

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Hyogo, Japan

Michio Nakajima