Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Synopsys, Inc.

Mitsubishi Denki Kaisha Kitaitami Seisakusho

Michio Komoda

Naoko Omori

Shigeru Kuriyama

Junya Shiraishi

Yoshio Inoue

Timothy N Ayres

Amitava Majumdar

Mitsuhiro Deguchi

Sigeru Kuriyama

A delay calculation method that is capable of calculating delay time with a small margin of error is provided for delay calculation in a logic circuit. The operating characteristics of transistor are expressed with a fixed resistance and a power supply voltage that changes with time. The power supply voltage is represented as a waveform which is a combination of two straight lines: the one indicating that the voltage, after a fixed delay of t, increases to Vduring &#x394;t; and the one indicating that the voltage increases from Vto E during &#x394;tand thereafter remains at the fixed value of E. A difference in the shapes of input waveforms is adopted as a correction parameter to determine the values of &#x394;t, V, and &#x394;t

Delay calculation method capable of calculating delay time with small margin of error

Regions Gto Geach including a predetermined number of flip-flops (FF) are divided into two groups. This dividing is performed so that the number of data connection channels intersected by a boundary is minimized. In the case of intersection of two data connection channels (A, A), the number of data connection channels intersected by the boundary is two, the minimum number. After grouping of all the regions (Gto GGto G), clock tree synthesis (CTS) is performed. If clock forming is performed in this way, the increase in clock skew on an actual device can be limited and on-chip variation resistance can be increased.

Clock forming method for semiconductor integrated circuit and program product for the method

The operating characteristic of a transistor, modeled by a resistive element having fixed resistance and a power source voltage that varies with time, is segmented into a linearity region in which a current increases as a gate potential varies and a saturation region in which the current gradually decreases as the gate potential remains at a constant level, so that gradual decrease in current in a saturation region of the transistor is properly reflected and a delay time is estimated in a precise manner.

Delay time estimation method and recording medium storing estimation program

The total resistance value of a coupling portion between first and second circuits is used as the resistance value of a load model; one-half of the total capacity value of the coupling portion is used as each coupling capacity value of the load model; the sum of one-half of the total earth capacity value of the coupling portion and the total capacity value of a non-coupling portion near a first circuit driver is used as the earth capacity value of the load model at a point near the first circuit driver; and the sum of one-half of the total earth capacity value of the coupling portion and the total capacity value of a non-coupling portion farther from the first circuit driver than the coupling portion is used as the earth capacity value of the load model at a point remote from the first circuit driver.

Method of formulating load model for glitch analysis and recording medium with the method recorded thereon

In accordance with a circuit modification method, when it is determined that an aggressor () causes a glitch error in a victim (), the one or more positions where one or more buffers are to be inserted into the victim () are determined based on the coupling capacity Cc between the victim () and the aggressor (). One or more buffers are inserted at one or more internal points of division of the victim () which are determined so that the coupling capacity between each of a plurality of wire segments, into which the victim is to be divided by the one or more internal points of division, and the aggressoris equal to Cc/n, where n is the number of wire segments. Furthermore, since the one or more buffers are inserted so that the coupling capacity Cc is properly divided into the coupling capacities between the plurality of wire segments and the aggressor, the amount of glitch to be caused in each of plurality of wire segment can be reduced and no further addition of buffers is needed.

Circuit modification method

A semiconductor integrated circuit includes a test pass and a test circuit that are placed on the way of the test pass so that a stage has the same excess value when the stage has different stage labels and different excess values in a scan chain of a stage interval n. A test pattern generation method for the semiconductor integrated circuit is also disclosed.

Semiconductor integrated circuit and test pattern generation method therefor

In cases where a delay time in a wire, which connects a first NAND placed on the upstream side and a second NAND placed on the downstream side, is calculated, there are a plurality of logical paths in the first NAND, and a parasitic capacitance of an output pin of the first NAND is determined for each logical path. Therefore, the parasitic capacitance corresponding to each logical path of the first NAND is separated from a fixed load model which indicates a sum of a load of the wire and a capacitance of an input pin of the second NAND, and the parasitic capacitance is added to the fixed load model in the calculation of the delay time. Accordingly, a load for the delay time calculation can be produced while precisely reflecting the parasitic capacitance changing with the logical path on the load production, and the delay time calculation can be performed with high accuracy.

Method of producing load for delay time calculation and recording medium

A wiring data generation method includes the steps of generating a line in a block of a first level, carrying out layout of the block of the first level in a block of a second level higher than the first level, and generating mesh lines of the block of the second level connected to the line in the block of the first level within the block of the second level.

Wiring data generation method and wiring data generation apparatus allowing inconsistency between block internal line and block external lines

A gate delay calculation apparatus includes an R parameter storage file for prestoring a parameter for expressing a source resistance value of an RC model as a continuous time function, an R determination portion for selectively extracting the parameter prestored in the R parameter storage file from the amount of input waveform gradient and output load model and a gate delay determination portion for calculating gate delay based on the source resistance value expressed by the parameter extracted by R determination portion and the output load model.

Gate delay calculation apparatus and method thereof using parameter expressing RC model source resistance value

In a semiconductor integrated circuit device, a clock buffer is arranged at the center of a chip by using a core I/O technique for arranging an input/output buffer at an arbitrary position. A clock is wired such that, with reference to a wire extending to a circuit in a chip which is farthest from the clock buffer and must be synchronously controlled. Wires extending to the other circuits are intentionally bypassed to make wires extending to all the circuits electrically equal to each other in length. Thus, a skew of a clock can be suppressed due to the isometric wiring.

Semiconductor integrated circuit device

A test circuit for DC testing which has a simple layout design and never causes malfunction due to simultaneous change of outputs includes test circuits connected to inputs of output allowable buffers. The test circuits are connected in a circle so that a value retained in each circuit can be applied to the adjacent test circuit. In the DC testing using the test circuit for DC testing, values which are retained in and output from output allowable buffers are circulated between the output allowable buffers. At the time, the values retained in the test circuit are changed within the range of the number allowable for simultaneous change.

Test circuit and method for DC testing LSI capable of preventing

A pipeline circuit with a test circuit in small circuit scale includes a pipeline circuit including a plurality of groups of flipflops arranged in series and a plurality of combinational circuits respectively arranged between the plurality of groups of flipflops and each having an input connected to an output of a group of flipflops at a previous stage and an output connected to a group of flipflops at a subsequent stage. The plurality of groups of flipflops include groups of flipflops subjected to scan conversion and groups of flipflops not subjected to scan conversion. The pipeline circuit, with a test circuit also includes a scan chain interconnecting the groups of flipflops subjected to scan conversion. An automatic test pattern generating method for testing the pipeline circuit with a test circuit, is also claimed.

Pipeline circuit with a test circuit with small circuit scale and an

The method of controlling ground bounce during DC parametric tests disclosed herein is based on the formulation of tests that best achieve two broad goals. The first goal is to reduce the number of I/O pins that are switched simultaneously. In the formulation of the VIL and VIH tests this goal is implemented by preferably only switching one input at a time. The second goal is to simultaneously switch I/O pins that are distant from one another. In the formulation of the VOL and VOH tests this goal is implemented by partitioning the outputs into subsets and selecting preferably one and only one output at a time from each and every subset.

Method for minimizing ground bounce during DC parametric tests using

A master slice LSI with fault detection circuitry includes a packed transistor area consisting of rows of semiconductor devices packed on a substrate. Parts of the rows are used for providing an application specific integrated circuit (ASIC). Remaining parts of the rows are used for providing fault detection circuitry for finding faulty semiconductor devices. The fault detection circuitry includes shift registers, sense amplifiers, and a decoder. The detection circuitry is provided only for those rows of semiconductor devices used for providing the intended purpose ASIC.

Master slice LSI with integrated fault detection circuitry

A multiplier circuit having a rounding-off function. A multiplier circuit has a smaller circuit size and operates at a higher speed by using a rounding half adder. An addition processing part which receives partial products from a partial product generating part, includes in its first stage two half adders and a rounding half adder. Its second stage includes three full adders, as does its third stage. Its fourth stage includes a three-bit carry look ahead adder. The output of the rounding half adder is the sum of the two inputs and an auxiliary value, such as 1. By utilizing the rounding half adder, a separate rounding circuit is unnecessary.

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Tokyo, Japan

Michio Komoda