Hitachi, Ltd.

Michio Hara

Toshiro Tsukada

Hisashi Tsuruoka

Hiroshi Takahashi

Kenji Kawakita

Katsuaki Takagi

Shunji Shimada

Kenji Iimura

Sakae Miki

Kenichi Kimura

Kenjirou Yasunari

Akira Ikuta

A system of adding an operand address included in an instruction word to the contents of a modification register to obtain an effective address, wherein address data which designates each of a plurality of data tables constituted with prescribed storage capacity, is stored in a plurality of modification registers. Prescribed address data of one of the plurality of modification registers is selected based on the instruction word. The effective address for addressing the operand is obtained by adding the prescribed address data of the one of the plurality of modification registers to address data included in the operand address. The address data included in the operand address designates addresses which correspond to addresses of the plurality of data tables.

Operand address modification system

An analog-to-digital converter comprising a capacitive element for storing an analog input signal, a discharge means for discharging the charge stored in said capacitive element, a means for counting the number of clockpulses between the time of discharge starting and the time at which the voltage at the output of said capacitive element reaches a certain detection level, and a bias voltage supply means for supplying a bias voltage in order to bring the voltage at the output terminal of said capacitive element at the discharge starting time above said detection level.

Analog-to-digital converter

An analog-to-digital converter comprising a capacitor for storing an analog input signal, a constant current discharging circuit coupled with the capacitor for discharging the charge stored therein, a level detection circuit connected to the input terminal of the capacitor, a counter connected to the output terminal of the level detection circuit for counting the number of clock-pulses between the time of discharge start and the time when the voltage at the input terminal of the capacitor drops to a detection level of the level detection circuit, a bias voltage supply means connected in series with the capacitor for adding a bias voltage to the voltage at the input terminal of said capacitor, and a switch connected in parallel with the capacitor for short-circuiting the capacitor when the voltage at the input terminal of said capacitor drops to the detection level.

Growing community of inventors

Kodaira, Japan

Michio Hara