Fujitsu Corporation

Nippon Telegraph and Telephone Corporation

Konishiroku Photo Industry Co., Ltd.

Michinobu Ohhata

Masao Yamasawa

Hisami Tanaka

Masayuki Takahashi

Takafumi Chujo

Hiroshi Nakaide

Hiroshi Takeo

Satoshi Takeda

Hiroshi Yamasaki

Masanori Kajiwara

Takao Moriya

Toshi Ikezawa

Kunihiko Goto

Masauki Takahasi

Toshihiko Matsumura

Ikuo Washiyama

Toshinari Kunieda

A digital signal transmission system includes a synchronization pattern detection circuit for detecting a synchronization pattern in response to a received transmitted digital signal, a pseudo synchronization detection circuit for detecting a pseudo synchronization pattern in the form of cyclic redundancy code in response to a received transmitted digital signal, and a synchronization protection circuit for counting the synchronization pattern detection signals produced when synchronization patterns are detected in response to a synchronization pattern detection signal from the synchronization pattern detection circuit. The synchronization protection circuit includes a main synchronization counter circuit and an auxiliary synchronization counter circuit. The count of protection steps for the confirmation of synchronization recovery of the auxiliary synchronization counter circuit in accordance with synchronization or asynchronization of the main synchronization counter circuit is variable.

Digital signal transmission system having frame synchronization operation

A sample and hold circuit for holding a sampled voltage, having a first MOS transistor for sampling the input voltage and a holding capacitor for holding the sampled voltage, and further comprising a second MOS transistor. The source and the drain of the second transistor are both connected to the output terminal of the circuit. The gate-source capacitance of the first MOS transistor is the sum of the gate-source and gate-drain capacitances of the second MOS transistor. When a voltage for turning on or off the first MOS transistor is applied to the gate of the first MOS transistor, the second MOS transistor is turned off or on respectively. The effect of this invention is that the sampled voltage can be held constant while turning off the first MOS transistor.

Sample and hold circuit

Offset compensating circuit

A codec, utilized for an PCM transmission system, has an a/d and d/a converter, and a digital phase locked loop circuit. The digital phase locked loop circuit generates internal operation clocks, which are used for the a/d and d/a converting operations, by dividing the frequency of the applied external clocks by a value determined in accordance with the frequency ratio between frame pulses and the external clocks.

A/D, D/A Converter for PCM transmission system

A digital-to-analog converter of the capacitive voltage divider type, which comprises an output conductor, a ground conductor, a power source conductor, an array of capacitors and an array of switches connected between said output conductor and either the ground conductor or the power source conductor, and which provides a high impedance element connected between said output conductor and the ground conductor.

Digital-to-analog converter

Growing community of inventors

Kawasaki, Japan

Michinobu Ohhata