Matsushita Electric Industrial Co., Ltd.

Renesas Technology Corp.

Michinari Yamanaka

Noboru Nomura

Masafumi Kubota

Kousaku Yano

Takeshi Yamashita

Susumu Matsumoto

Tomoyasu Murakami

Mitsuru Sekiguchi

Masayuki Endo

Takayuki Yamada

Tetsuya Ueda

Hiroshi Imai

Hiroaki Nakaoka

Shigenori Hayashi

Kenji Harafuji

Hiroshi Yuasa

Naoto Matsuo

Shuji Hirao

Junjiro Sakai

Yasutaka Nishioka

Tetsuo Satake

Etsuyoshi Kobori

Shingo Tomohisa

Fumio Iwamoto

Staoshi Ueda

After a hole is formed in a low dielectric constant film on a substrate, a protective film is formed on the wall surface of the hole or an electron acceptor is caused to be adsorbed by or implanted in the low dielectric constant film exposed at the wall surface of the hole. Otherwise, resist residue is left on the wall surface of the hole. Then, a resist pattern having an opening corresponding to a wire formation region including a region formed with the hole is formed by using a chemically amplified resist.

Method for fabricating electronic device

It is an object to provide a semiconductor device having a buried multilayer wiring structure in which generation of a resolution defect of a resist pattern is suppressed and generation of a defective wiring caused by the resolution defect is reduced. After a via hole () reaching an etching stopper film () is formed, annealing is carried out at 300 to 400&#xb0; C. with the via hole () opened. As an annealing method, it is possible to use both a method using a hot plate and a method using a heat treating furnace. In order to suppress an influence on a lower wiring () which has been manufactured, heating is carried out for a short time of approximately 5 to 10 minutes by using the hot plate. Consequently, a by-product staying in an interface of an upper protective film () and an interlayer dielectric film () having a low dielectric constant and a by-product staying in an interface of the etching stopper film () and the interlayer dielectric film () having a low dielectric constant are discharged so that an amount of the residual by-product can be decreased.

Electronic device manufacturing method

A method for evaluating an insulating film includes: a first step of forming an insulating film on a semiconductor substrate including a p-n junction therein; a second step of selectively forming an electrode pattern on the insulating film; a third step of forming a measurement electrode on the insulating film so as to be electrically insulated from the electrode pattern; and a fourth step of applying a measurement voltage between the measurement electrode and the semiconductor substrate via the insulating film and measuring a leakage current leaking through the p-n junction so as to evaluate a damage to the insulating film or the semiconductor substrate.

Evaluation method for evaluating insulating film, evaluation device therefor and method for manufacturing evaluation device

After formation of a connection hole or before deposition of an insulator film, a semiconductor device is placed onto a cathode of a plasma generator. A surface of a metal silicide film such as a silicide of titanium is exposed to a plasma of a nitrogen-containing gas at 550 degrees centigrade or less. As a result of such processing, a barrier compound layer, composed of a compound of nitrogen, oxygen, metal and silicon, is formed at a near-surface region of the metal silicide film of the titanium silicide film. Thereafter, while forming a buried layer from material superior in step coverage such as an Al--Ti compound and an aluminum alloy, reaction between the metal silicide film and the buried layer in a later annealing treatment can be avoided without depositing a barrier metal such as a titanium nitride/nitride film in the connection hole. Accordingly, contact resistance, sheet resistance and junction leakage can be reduced and reliability can be improved.

Semiconductor device having improved lamination-structure reliability

A reactive gas supplied to a chamber 1 is put into plasma by supplying radio frequency power to the chamber 1 intermittently or while repeating high and low levels alternately and a specimen A in the chamber 1 is treated by the plasma. A positive pulse-like bias voltage synchronized with a period in which the radio frequency power is not supplied or a period in which low-level power is supplied is applied to the specimen A for preventing charging.

Plasma treatment method and plasma treatment system

In a dry etching method of aluminum (Al) alloy film comprising the steps of (1) forming an alloy film of which a major component is Al on a semiconductor substrate, (2) forming a resist pattern on the alloy film, and (3) dry etching the alloy film using the resist pattern as a mask with etching gas to which ammonia gas is added, a flow rate of the ammonia gas being set at between not less than half of a flow rate of the etching gas and not more than the flow rate of the etching gas. Improved fine pattern dry etching of Al alloy including Si and Cu is achieved.

Dry etching method for aluminum alloy and etching gas therefor

Through exposure of the top surface of a tungsten film to plasma of a gas including nitrogen at a temperature of 550.degree. C. or less, a tungsten nitride layer having a structure in which nitrogen atoms and tungsten atoms are bonded is formed in an area in the vicinity of the surface of the tungsten film. Then, an aluminum alloy film is deposited on the tungsten film, thereby forming a metallic interconnection. Since the nitrogen atoms and the tungsten atoms are bonded in the tungsten nitride layer formed by such plasma nitridation, the tungsten nitric layer not only has a good barrier function to prevent the diffusion of other metal atoms but also can be formed in a small thickness. Accordingly, formation of an alloy layer with a high resistance otherwise caused due to counter diffusion during an annealing process and a junction leakage can be avoided.

Semiconductor apparatus with tungstein nitride

After accumulating a BPSG film layer on a silicon substrate, a first Al--Si--Cu film layer, a W film layer and a second Al--Si--Cu film layer are successively accumulated on this BPSG film layer. A resist pattern with wide-width and narrow-width pattern portions is formed on the second Al--Si--Cu film layer. The wide-width pattern portion is provided at a position corresponding to a contact for connecting a first-layer metallic wiring and a second-layer metallic wiring, while the narrow-width pattern portion is provided at a position corresponding to a wiring portion for the first-layer metallic wiring. After applying first etching on the second Al--Si--Cu film layer with a mask of the resist patter, second etching is applied on the W film layer. Thereafter, by applying third etching, the resist pattern remaining on the first-layer metallic wiring is removed and the first Al--Si--Cu film layer is transfigured into a tall metallic film portion and a short metallic film portion. After accumulating an inter-layer insulating film layer on the first Al--Si--Cu film layer, etchback is applied on this inter-layer insulating film layer until the top of the tall metallic film portion is bared. Then, the second-layer metallic wiring is formed on the inter-layer insulating film layer so that the second-layer metallic wiring is connected with the tall metallic film portion.

Method for forming a multi-layer metallic wiring structure

According to the method of preventing the corrosion of metallic wirings of the present invention, aluminium alloy wirings are formed on the surface of a substrate with the use of photoresists, and the photoresists are then removed. Thereafter, HMDS (hexamethyl disilazine) serving as a surface-active agent or its derivative is supplied to the aluminium alloy wirings to form hydrophobic molecular layers on the lateral walls of the aluminium alloy wirings.

Method of preventing the corrosion of metallic wirings

Growing community of inventors

Osaka, Japan

Michinari Yamanaka