Nara Institute of Science and Technology

Kyushu Institute of Technology

Tokyo Metropolitan University

Michiko Inoue

Yasuo Sato

Tomokazu Yoneda

Hiroshi Iwata

Seiji Kajihara

Satoshi Ohtake

Hyunbean Yi

Yukiya Miura

A scan asynchronous memory element includes: an asynchronous memory element configured to receive an n-input; and a scan control logic circuit configured to generate an n-bit signal input and the n-input to the asynchronous memory element from a scan input. The scan control logic circuit outputs the signal input when a control signal supplied to the scan control logic circuit has a first bit pattern, the scan control logic circuit outputs the scan input when the control signal has a second bit pattern, and the scan control logic circuit outputs a bit pattern allowing the asynchronous memory element to hold a previous value when the control signal has a bit pattern other than the first and second bit patterns.

Asynchronous memory element for scanning

A semiconductor device and the like that can determine the performance of a semiconductor integrated circuit with higher accuracy even when test environment fluctuates. The semiconductor device detects degradation of the semiconductor integrated circuit, including measurement unit that measures temperature and voltage, decision unit that judges whether the test is executed within an allowable test timing in the detection target circuit portion at each test operation frequency and decides a maximum test operation frequency and calculation unit that converts a maximum test operation frequency into that at a standard temperature and voltage and calculates a degradation amount. The semiconductor integrated circuit has a monitor block circuit that monitors the values for the measurement unit to measure temperature and voltage. The measurement unit has estimation unit that estimates temperature and voltage of a detection target circuit portion based on the monitored values. The calculation unit uses the estimated temperature and voltage.

Semiconductor device, detection method and program

A test pattern is sequentially selected from an original test pattern sequence constituted by a plurality of test patterns including a don't care bit. Power consumption in each of regions obtained by substantially equally dividing a layout region of a semiconductor integrated circuit in a case where a don't care value is specified in the selected test pattern and this selected test pattern is applied to the semiconductor integrated circuit is estimated. A searching is conducted for a don't care value of the selected test pattern which minimizes a variation in power consumption among the regions by repeatedly changing the don't care value and repeatedly estimating power consumption in the regions. A new test pattern sequence constituted by a plurality of test patterns including no don't care bit is generated by defining the don't care value obtained by the searching as a don't care value of the selected test pattern.

Test pattern generation for semiconductor integrated circuit

Growing community of inventors

Nara, Japan

Michiko Inoue