Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electronics Corporation

Michikazu Matsumoto

Naohisa Sengoku

Mizuki Segawa

Toshiki Yabu

Yasutoshi Okuno

Takayuki Yamada

Takaaki Ukeda

Takashi Nakabayashi

Takashi Uehara

Masatoshi Arai

Kyoji Yamashita

Isao Miyanaga

Masahiro Yasumi

Hiroshi Iwai

Kazuhiko Hashimoto

Teruhito Ohnishi

Masafumi Kubota

Masahiro Fukui

Hiroyuki Umimoto

Yukihisa Wada

Takehiro Hirai

Susumu Akamatsu

Yuichi Miyoshi

Shinichi Ogawa

Toshiro Akino

Tatsuo Sugiyama

Kuniyuki Kakushima

Satoe Miyata

Masato Kanazawa

Minoru Fujii

Tetsuya Matsutani

Kazuo Tsutsui

Kouji Tamura

Seiji Ueda

Katsuyoshi Joukyu

Ayumi Kobayashi

A method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; removing part of the first insulating film; forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the part of the first insulating film has been removed on the semiconductor substrate; forming an undoped semiconductor film on the first and second insulating films; implanting an impurity into part of the undoped semiconductor film, thereby defining semiconductor regions of a first conductivity type dotted as discrete islands; forming a third insulating film on the semiconductor regions of the first conductivity type and the undoped semiconductor film; and removing part of the third insulating film by wet etching. At least the second insulating film is formed under the semiconductor regions of the first conductivity type.

Semiconductor device and method for fabricating the same

A gate electrode is formed on a semiconductor substrate containing silicon, then source/drain regions are formed in regions of the semiconductor substrate located to both sides of the gate electrode, and then a nickel alloy silicide layer is formed on at least either the gate electrode or the source/drain regions. In the step of forming the nickel alloy silicide layer, a nickel alloy film and a nickel film are sequentially deposited on the semiconductor substrate and thereafter subjected to heat treatment.

A gate electrode is formed on a silicon substrate, and then source/drain regions are formed at both sides of the gate electrode in the silicon substrate. Thereafter, an alloyed silicide layer is formed on the source/drain regions. The step of forming the alloyed silicide layer includes the step of depositing a first metal film, a nickel film and a second metal film in this order to form a multilayer metal film and the step of performing heat treatment after the formation of the multilayer metal film.

A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a component of an integrated circuit device, the resistance defect assessment device including test patterns capable of measuring a resistance variation component to be the resistance variation defect in each chip area or each shot area of the wafer, wherein the number of test patterns included in one chip area or one shot area is set so that it is possible to estimate the yield of the integrated circuit device.

Resistance defect assessment device, resistance defect assessment method, and method for manufacturing resistance defect assessment device

A semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having a formation enthalpy lower than that of NiSi and a second silicide layer formed on the first silicide and made of Ni silicide.

An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

Semiconductor device and method of manufacturing the same

A wafer for charge amount evaluation having a silicon substrate and p-type regions sandwiched between a first silicon oxide film and a SA-NSG film and surrounded by an undoped silicon film is prepared and subjected to a target process for which an amount of charge is to be evaluated. Then, etching is performed by using a BHF solution. By measuring an amount of etching in the p-type region, an amount of positive charge caused by the process in the wafer can be evaluated quantitatively in an easy and convenient manner.

Apparatus for evaluating amount of charge, method for fabricating the same, and method for evaluating amount of charge

The electrode structure of this invention includes a silicon-containing film containing silicon as a principal constituent; a barrier metal layer of titanium nitride rich in titanium as compared with a stoichiometric ratio formed on the silicon-containing film; and a metal film with a high melting point formed on the barrier metal layer.

Electrode structure and method for fabricating the same

In a method for manufacturing a semiconductor device, impurity ion is implanted into a semiconductor layer so as to form an ion implantation region in the semiconductor layer, and at least the ion implantation region is turned amorphous. Then, an insulating film is formed on the semiconductor layer at a temperature at which the ion implantation region is not crystallized, and then the semiconductor layer is annealed in a non-oxidizing atmosphere so as to activate the impurity ion implanted into the semiconductor layer.

Method for manufacturing semiconductor device

An electronic device having a component containing a refractory metal such as tungsten is cleaned by using a cleaning solution composed of an acidic solution which does not substantially contain aqueous hydrogen peroxide or an alkaline solution which does not substantially contain aqueous hydrogen peroxide.

Method of cleaning electronic device and method of fabricating the same

Ions of boron as a dopant are implanted using a gate electrode and an isolation film as a mask, thereby forming an ion-implanted layer as a prototype for an extended heavily doped layer. In this process step, a peak concentration of the dopant existing in the ion-implanted layer is set close to, and equal to or less than, a solid solubility at a process temperature for a first annealing process. Then, almost all of the dopant existing in the extended heavily doped layer is activated by performing the first annealing process. Thereafter, a sidewall and an ion-implanted layer as a prototype for a heavily doped source/drain layer are formed, and then the heavily doped source/drain layer is defined by performing a second RTA process.

A first metal film of a first metal is deposited on a silicon-containing film containing silicon as a principal constituent, and a second metal film of a nitride of a second metal is deposited on the first metal film. Thereafter, a metal film with a high melting point is deposited on the second metal film, so as to form a multi-layer film of the silicon-containing film, the first metal film, the second metal film and the metal film with a high melting point. The multi-layer film is then subjected to annealing at a temperature of 750&deg; C. or more. In this case, the first metal is nitrided to be changed into a nitride of the first metal and a silicide layer of the first metal is not formed in a surface portion of the silicon-containing film before the annealing.

Method for fabricating electrode structure and method for fabricating semiconductor device

After depositing a first metal film of a first metal on a silicon-containing film including silicon as a main component, a second metal film of a nitride of a second metal is deposited on the first metal film. Then, a high-melting-point metal film is deposited on the second metal film, so as to form an electrode structure including the silicon-containing film, the first metal film, the second metal film and the high-melting-point metal film. The electrode structure is then subjected to a heat treatment at 750&deg; C. or more. The first metal film has such a thickness that the first metal is nitrided to be changed into a nitride of the first metal and a silicide layer of the first metal is not formed in a surface portion of the silicon-containing film after the heat treatment.

Growing community of inventors

Kyoto, Japan

Michikazu Matsumoto