Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Michihiro Mishima

Takeshi Wada

Susumu Hatano

Yasushi Takahashi

Masayasu Kawamura

Shin'ichi Ikenaga

Fujio Yamamoto

Kenji Nishimoto

Jun Kitano

Herein disclosed is a semiconductor integrated circuit for testing test data of two kinds of non-inverted and inverted statuses of all bits by itself with a prospective data of one kind to compress and output the test results. The semiconductor integrated circuit includes a decide circuit 25 for deciding a first status, in which the prospective data latched by a pattern register and the read data of a memory cell array are coincident, a second status, in which the read data is coincident with the logically inverted data of the prospective data, and a third statuses other than the first and second statuses through an exclusive OR gate to generate signals of 2 bits capable of discriminating the individual statuses. These statuses are informed to the outside of the semiconductor integrated circuit in accordance with high- and low-levels and a high-impedance.

Semiconductor memory device

Growing community of inventors

Kodaira, Japan

Michihiro Mishima