Matsushita Electric Industrial Co., Ltd.

Michihiro Inoue

Toshio Yamada

Takeji Kimura

Masaharu Sato

Toyoki Takemoto

Shozo Okada

Naoto Matsuo

Masahiko Tsunoo

Akira Matsuzawa

Haruyasu Yamada

Atsushi Fujiwara

Kazuhiro Matsuyama

Hiroyuki Yamauchi

Toshiki Yabu

Tadao Komeda

Akihiro Kanda

Hideaki Sadamatsu

Namio Hirose

Junko Hasegawa

Shiro Horiuchi

Akira Matzuzawa

Takashi Ozone

The present invention comprises a plurality of semiconductor testing circuit chips 2 having an exclusive function of testing a plurality of one item of semiconductor integrated-circuit chips 1, a computer 3 for controlling the semiconductor testing circuit chips 2 and for collecting the test results, and a motherboard 4 on which the plurality of chips 1 to be tested and the plurality of testing circuit chips 2 are mounted so that the chips 1 to be tested are connected to the testing circuit chips 2. Since the major testing functions are incorporated into the testing circuit chips 2, the computer 3 for collecting the test results can sufficiently be composed of a low-price computer, so that it is possible to greatly lower the price of the semiconductor testing apparatus. By increasing the number of the testing circuit chips 2, it is possible to greatly increase the number of chips which can be tested simultaneously. Consequently, there can be provided a semiconductor testing apparatus which realizes the reduction in price and the increase in number of the semiconductor integrated circuits tested simultaneously, thereby significantly reducing the cost of testing the semiconductor integrated circuits.

Semiconductor testing apparatus, semiconductor testing circuit chip, and

A dynamic random access memory is formed with two power supply meshes extending throughout a memory array region in which are formed memory cells and sense amplifier circuits, thereby enabling sense amplifier drive circuits to be distributed throughout that memory array region, with each sense amplifier drive circuit being connected to the nearest points on the two supply meshes. A substantially improved value of read access time, or increased total memory capacity, can thereby be achieved by comparison with a DRAM in which the sense amplifier drive circuits are provided only at the periphery of a memory array region.

Semiconductor memory apparatus with reduced line widths

A semiconductor memory device is provided which includes a semiconductor substrate of a first conductivity type, a plurality of trench capacitors formed in the substrate and a plurality of switching transistors formed on the respective trench capacitors. Each of the switching transistors is electrically connected to the corresponding trench capacitor. Each of the trench capacitors has a first electrode formed in the side portion of a trench provided in the substrate and a second electrode containing impurities of the first conductivity type and embedded in the trench. Each of the switching transistors has a source region formed from a first epitaxial layer of the first conductivity type grown on the trench so as to electrically contact the second electrode, a channel region formed from a second epitaxial layer of a second conductivity type grown on the first epitaxial layer, and a drain region formed from a third epitaxial layer of the first conductivity type grown on the second epitaxial layer. The first, second and third epitaxial layers are in contact with a polycrystalline silicon layer containing impurities of the second conductivity type. The first conductivity type is opposite to the second conductivity type.

Method of producing a semiconductor device having trench capacitors and

Semiconductor memory device and a method for producing the same

In a semiconductor memory device comprising memory cells in which first and second potentials correspond to the logic values '0' and '1', the first potential is closer to the second potential than the potential of unselected word lines, by 0.3 V or more. The pull-up transistor is of the N-type, and the pull-down transistor is of the P-type.

Semiconductor memory device

Semiconductor memory drive

Disclosed is a semiconductor memory device comprising a semiconductor substrate on which memory cells are formed, each including a switching transistor formed on the semiconductor substrate and a capacitor disposed above the switching transistor. The capacitor has a storage electrode, a cell plate and a capacitor insulating film sandwiched therebetween. The storage electrodes of at least two adjacent memory cells are partly disposed one above the other, with part of the cell plate interposed therebetween. Also disclosed is a semiconductor memory device in which the capacitors of the memory cells are disposed in a trench formed in the semiconductor substrate. The two switching transistors of two adjacent memory cells are located on each island-shaped active region surrounded by the trench. The storage electrodes of the capacitors of the two adjacent memory cells extend side by side around the corresponding active region, with part of the cell plate interposed between the storage electrodes.

A dynamic random access memory which includes a memory cell array, sense amplifiers disposed at both side of the memory cell array, and sub bit lines coupled to the sense amplifiers. The sub bit lines are coupled to data busses through middle amplifiers. By use of such memory architecture, higher integration of DRAM can be realized. Also, handling of super large bit data more than 1024 bit becomes possible.

Semiconductor memory device having sub bit lines

A dynamic random access memory which includes a sense amplifier, first pair of bit lines extending in the opposite directions from the sense amplifier, second pair of bit lines extending in the opposite directions from the sense amplifier and disposed in parallel with the first pair of bit lines, a plurality of word lines disposed in a manner that the word lines perpendicularly intersect with the first and second pairs of bit lines, and a plurality of memory cells disposed at all intersecting points of the word lines and the first and second pairs of bit lines. Two bit lines selected from the first and second pairs of bit lines are coupled to the sense amplifier. Since two bit lines or two groups of memory cells can be disposed at one side of the sense amplifier, space efficiency can be highly improved without damaging the operating characteristics of a dynamic random access memory.

Dynamic random access memory having open bit line architecture

A dynamic random access memory includes a memory cell array, sense amplifiers disposed at both sides of the memory cell array, and sub bit lines coupled to the sense amplifiers. The sub bit lines may be coupled to data busses through middle amplifiers. By use of such a memory architecture, a higher integration of a DRAM can be realized. Also, the handling of super large bit data, i.e. more than 1024 bits becomes possible.

Seimiconductor memory device having sub bit lines

A method of fabricating a field effect transistor, wherein impurity diffusion layers of source and drain are formed by an ion implantation method using the gate electrode as the mask by inclining the semiconductor substrate with respect to the ion beam incident direction so as to prevent the channeling effect and also rotating it in planarity with respect to the ion beam scanning plane. As a result, impurity diffusion layers can be formed symmetrically with respect to the gate electrode.

Method of making symmetrically controlled implanted regions using

In a serial-type A/D converter utilizing folding circuit cells connected in cascade, the cell has a differential type input and a differential type output, and a comparator included in the cell switches over current paths in the cell to establish a folding characteristic. An input potential difference is converted into a current difference by a pair of transistors having the emitters interconnected through a resistor, and the current difference is further converted into a pair of differential output voltages by a load circuit having a pair of series connections each including a resistor, a diode and a transistor having its base connected with another resistor, so that the non-linear characteristic and gain can be corrected. A current switching circuit is switched by the comparator for discriminating the polarity of the input potential difference to switch over current paths for the paired transistors or to alternately operate voltage level shifting circuits associated with a pair of output terminals, thereby establishing the folding characteristic with high accuracy.

Serial-type A/D converter utilizing folding circuit cells

In making a vertical bipolar transistors, after forming by diffusion process a region to become inactive base region an oxide film is selectively formed on the region, thereafter an ion implantation is carried out to produce regions which become the active base region and emitter region by using the oxide film; thereby such a configuration is formed so that defect part (108) induced at the time of the ion implantation is confined in the emitter region, thereby minimizing the leakage current at the PN junction, and hence assuring production of high performance and high reliability semiconductor devices; further, a high integration is attained by adopting self-alignment in forming emitter contact.

Method for making semiconductor device

A parallel type analog-digital converter having a plural number (1023) of comparators, a first voltage divider comprising a plural number (1023) of resistors (R.sub.1 to R.sub.1023) connected in series across positive and negative terminals of a power source thereby feeding reference voltages from the junction points to the comparators, the apparatus further comprises

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Ikoma, Japan

Michihiro Inoue