Nxp B.v.

Koninklijke Philips Corporation N.v.

Michiel Jos Van Duuren

Robertus Theodorus Fransiscus Van Schaijk

Pierre Hermanus Woerlee

Youri Victorovitch Ponomarev

Franciscus Petrus Widdershoven

Abraham Rudolf Balkenende

Prabhat Agarwal

Martijn Henri Richard Lankhorst

Jacob Christopher Hooker

Erik Petrus Antonius Maria Bakkers

Louis Felix Feiner

The electric device () according to the invention comprises a layer () of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device () further comprises a set of nanowires (NW) electrically connecting a first terminal () of the electric device and the layer () of memory material thereby enabling conduction of an electric current from the first terminal via the nanowires (NW) and the layer () of memory material to a second terminal () of the electric device. Each nanowire (NW) electrically contacts the layer () of memory material in a respective contact area. All contact areas are substantially identical. The method according to the invention is suited to manufacture the electric device () according to the invention.

Electric device with a layer of conductive material contacted by nanowires

The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface (), and a device thus manufactured. The method comprises:&#x2014;forming, on the substrate surface, a stack comprising an insulating film (), a first layer of floating gate material () and a layer of sacrificial material (),&#x2014;forming at least one isolation zone () through the stack and into the substrate (), the first layer of floating gate material () thereby having a top surface and side walls (),&#x2014;removing the sacrificial material (), thus leaving a cavity () defined by the isolation zones () and the top surface of the first layer of floating gate material (), and filling the cavity () with a second layer of floating gate material (), the first layer of floating gate material () and the second layer of floating gate material () thus forming together a floating-gate ().

Shallow trench isolation in floating gate devices

The present invention describes a method for operating an array of nonvolatile charge trapping memory devices. The method comprises before a block erase step () of substantially all of the non-volatile memory devices of the array, block programming () of substantially all of the non-volatile memory devices of the array. It is an advantage of the present invention that, by doing this, a further charge trapping nonvolatile memory device may be used as a reference cell, which is programmed and erased with the block-programming and block-erasing of the memory cells in the array, so that the reference cell shows the same cycling history as the memory cells in the array. This feature can be used for adapting read parameters to ageing of the memory cells. Corresponding devices are also provided.

Erase and read schemes for charge trapping non-volatile memories

The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (), a control gate () and a separate erase gate (). The erase gate () is provided in or on isolation zones () provided in the substrate (). Because of that, the erase gates () do not add to the cell size. The capacitance between the erase gate () and the floating gate () is small compared with the capacitance between the control gate () and the floating gate (), and the charged floating gate () is erased by Fowler-Nordheim tunneling through the oxide layer between the erase gate () and the floating gate ().

Non-volatile memory with erase gate on isolation zones

In the method for manufacturing a semiconductor device (), which comprises a semiconducting body () having a surface () with a source region () and a drain region () defining a channel direction () and a channel region (), a first stack () of layers on top of the channel region (), the first stack () comprising, in this order, a tunnel dielectric layer (), a charge storage layer () for storing an electric charge and a control gate layer (), and a second stack () of layers on top of the channel region () directly adjacent to the first stack () in the channel direction (), the second stack () comprising an access gate layer () electrically insulated from the semiconducting body () and from the first stack (), initially a first sacrificial layer () is used, which is later replaced by the control gate layer (). A second sacrificial layer () is used to protect the part () off the surface () adjacent to the second sidewall () and opposite to the position () of the second stack () when providing the access gate layer ().

Method of manufacturing a semiconductor device

Fabrication of a memory cell, the cell including a first floating gate stack (A), a second floating gate stack (B) and an intermediate access gate (AG), the floating gate stacks (A, B) including a first gate oxide (), a floating gate (FG), a control gate (CG; CGl, CGu), an interpoly dielectric layer (), a capping layer () and side-wall spacers (), the cell further including source and drain contacts (), wherein the fabrication includes: defining the floating gate stacks in the same processing steps to have equal heights; depositing over the floating gate stacks a poly-Si layer () with a larger thickness than the floating gate stacks' height; planarizing the poly-Si layer (); defining the intermediate access gate (AG) in the planarized poly-Si layer () by means of an access gate masking step over the poly-Si layer between the floating gate stacks and a poly-Si etching step.

Self-aligned 2-bit 'double poly CMP' flash memory cell

A method to improve the coupling ratio between a control gate () and a floating gate () of a floating gate non-volatile semiconductor device is described. In a stacked gate floating gate transistor according to the invention, a conductive spacer () is used at both sides of the stack. The conductive spacer () is galvanically connected to the control gate (), preferably by means of a conductive layer (), whereas it is separated from the floating gate () by means of an insulating layer (). The capacitance (C, C) between both conductive spacers () and the side walls of the floating gate () adds up to the normal capacitance between control gate () and floating gate ().

Growing community of inventors

Leuven, Belgium

Michiel Jos Van Duuren