Texas Instruments Corporation

Michiel De Wit

Richard K Hester

Khen-Sang Tan

Roddy Fro Hotz

An analog-to-digital converter has a binary weighted capacitor array with one plate of each capacitor connected at an input to a comparator and successive approximation logic circuitry provided for selectively connecting the capacitors to high reference, low reference or analog input signal voltage to develop a digital output in a successive charge redistribution conversion process. An on-board test data generator provides a test input voltage signal for a test mode. The other plate of each capacitor is selectively connected to the high or low reference voltage to charge the capacitors separately according to a prestored or externally supplied test pattern sequence. The digital output obtained from applying the usual sample, hold and charge redistribution process to the internally supplied test signal is compared to an expected digital output for an input signal corresponding to the predetermined test pattern sequence.

Self-test for charge redistribution analog-to-digital converter

An analog-to-digital conversion system (6) is provided which includes an analog-to-digital converter (8) having a first node (NODE 1) and a second node (NODE 2). An automatic offset tracking and correcting circuit (10) is coupled to the first node (NODE 1) and the second node (NODE 2).

Automatic offset tracking and correcting circuit and method of operation

A resistor circuit (and structure) 10 is disclosed herein. A first resistor 14 has a first temperature coefficient of resistance and is coupled to a second resistor 16 which has a second temperature coefficient of resistance, typically opposite to the first temperature coefficient of resistance. The resistors 14 and 16 are coupled together (e.g., in series or in parallel) to create a total resistor with a predetermined (e.g., substantially zero) temperature coefficient of resistance.

Temperature independent resistor

A differential fuse circuit 10 is disclosed herein. A first fuse 12 and a second fuse 14 are coupled to a supply potential V.sub.DD (e.g., five volts). Circuitry 16 and 18 for blowing the two fuses 12 and 14 is also provided. A current mirror 46 including a first leg and a second leg is also provided. The current mirror 46 is designed so that a current through the first leg will induce a current in the second leg. The first leg is coupled between the first fuse 12 and a reference potential V.sub.SS and the second leg is coupled between the second fuse 14 and the reference potential V.sub.SS. An output node 56 is provided between the second fuse 14 and the second leg of the current mirror 46. A differential sense circuit 24 may also be included between the fuses 12 and 14 and the current mirror 46. During operation, the output node is at a potential substantially near the reference potential when the first fuse has a resistance greater than the second fuse and the output node is at a potential substantially near the supply potential when the first fuse has a resistance less than the second fuse. Other systems and methods are also disclosed.

Differential fuse circuit and method utilized in an analog to digital

A capacitor array circuit is disclosed herein. A main capacitor array includes at least a most significant array portion 12 and a least significant array portion 14. A coupling capacitor C.sub.C is formed between the two portions of the array. Typically, one plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the least significant array portion 14 and a second plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the most significant array portion 12. A variable calibration capacitor C.sub.CAL is also provided. In a preferred embodiment, the variable calibration capacitor C.sub.CAL is coupled between the coupling capacitor C.sub.C and an AC ground node. In alternate embodiment, the variable calibration capacitor C.sub.CAL is coupled in parallel with the coupling capacitor C.sub.C. In the preferred embodiment, the variable calibration capacitor C.sub.CAL comprises array 26 of calibration capacitors 28a-28n, each associated with a switch element 30a- 30n. The array 26 may be a binary weighted array.

Circuit and method for tuning capacitor arrays

A sample and hold circuit (24) is provided which includes an input terminal (36) for receiving a time varying input voltage. A first capacitor (14) maintains a first voltage corresponding to a sample of said time varying input voltage. A switch (12) having a control terminal (20) is operable to sample the input voltage by coupling input terminal (36) to first capacitor (14) in response to a sampling signal provided at control terminal (20). At least one second capacitor (58, 86) is provided for maintaining a preselected voltage. Circuitry (40, 42, 68, 106) is provided for selectively applying the sampling signal to control terminal (20) of switch (12) by impressing at least the preselected voltage maintained by second capacitor (58, 86) on control terminal (20).

Sample and hold circuitry and methods

An A/D converter includes a positive array of binary weighted capacitors with a common top plate (12) and a negative array of binary weighted capacitors with a common top plate (32). The positive and negative arrays are input to a differential amplifier (10) for measuring the differential voltage across the top plates. During the sample time, a differential input voltage is sampled on the bottom plates of the capacitors and the top plates of the capacitors are disposed at the common mode voltage of the input signal. This limits the input voltage across the capacitors to one-half the differential voltages of the input signal. During the hold mode and the redistribution mode, this presents a predetermined common mode input voltage to the amplifier (10) which is independent of the input signal.

Charge redistribution A/D converter with increased common mode rejection

An improved optically pumped, acousto-optically Q-switched laser is disclosed, capable of significantly increased output energy. Optical coatings, with their inherent limitations on maximum energy of the output pulse, are completely eliminated. At the reflecting surfaces, Porro prisms replace the mirrors conventionally used. At the non-reflecting or transmitting surfaces, conventional, anti-reflective coatings are eliminated by placing the respective elements at the Brewster angle for the dominant polarization of the Q-switching material. Optimum output coupling is achieved by adjustment of the Q-switch drive. In order to prevent undesired second pulses in the output, which normally limit the maximum attainable output energy, a filtering shield of material opaque to the operating frequency is placed in the laser cavity, between the flash pump and the laser rod, to minimize the possibility of a second-pulse buildup due to random emission before the Q-switch is turned fully off. The wavelength of the output radiation may be sequentially selected from among the various spectral lines of the lasing material, by appropriate selection of the RF frequency applied to the acousto-optic element.

Method of preventing post pulsing of Q-switched laser

A techinque for modulating the output signal of an acousto-optically Q-switched laser is disclosed. The switch is energized with an acoustic wave having a frequency equal to the approximate frequency spacing between longitudinal lasing modes of the laser. Among other advantages, the technique permits identification of lasers by length of resonator and through detection of the frequency of modulation of the laser output.

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Dallas, TX, United States of America

Michiel De Wit