Hitachi, Ltd.

Hitachi Microcomputer System, Ltd.

Michiaki Nakayama

Kazutaka Mori

Hideo Sawamoto

Satoru Isomura

Mitsugu Kusunoki

Masato Hamamoto

Toru Kobayashi

Yuji Yokoyama

Shuichi Miyaoka

Shuuichi Miyaoka

Hideki Sakakibara

Kouji Kobayashi

Takashi Ogata

Masato Ikeda

Masanori Odaka

Kazuhisa Miyamoto

Masao Kato

Masaji Kume

Tsutomu Sumimoto

Masatoshi Hasegawa

Masatoshi Sakamoto

Kazumasa Takashima

Nobutaka Itoh

A semiconductor integrated circuit device including a memory circuit with both high access efficiency and high memory efficiency in a simple configuration is provided. In a memory read control circuit, burst length is changed based on whether or not a read instruction is issued at a cycle after a cycle at which a read instruction /R is issued. And, in a memory write control circuit, burst length is changed based on whether or not a write instruction is issued at a cycle before a cycle at which a write instruction /W is issued.

Synchronous memory circuit

An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type welland the p-type wellfrom an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type welland the p-type wellto the voltages Vdd and Vss, respectively.

Semiconductor integrated circuit

Read buffers (RB -RB ) are capable of holding data read out from a plurality of memory blocks (BNK -BNK ) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means ( ) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.

Semiconductor integrated circuit device with memory blocks and a write buffer capable of storing write data from an external interface

An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well , in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well , in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well and the p-type well from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well and the p-type well to the voltages Vdd and Vss, respectively.

Semiconductor integrated circuit and its fabrication method

Semiconductor integrated circuit device with memory banks and read buffer capable of storing data read out from one memory bank when data of another memory bank is outputting

To provide a semiconductor integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which one transistor Tp for constituting the CMOS circuit is set, with a first power-supply-voltage line Vdd through a switching transistor Tps, and electrically connecting a p-type well 3 in which the other transistor Tn for constituting the CMOS circuit is set with a second power-supply-voltage line Vss through a switching transistor Tns. Moreover, the semiconductor integrated circuit is constituted so that thermal runaway due to leakage current can be controlled by turning off the switching transistors Tps and Tns and supplying a potential suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the semiconductor integrated circuit is being tested. Furthermore, the semiconductor integrated circuit is constituted so that fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on the switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the power supply voltages Vdd and Vss, respectively.

Semiconductor integrated circuit device and process for manufacturing the same

A semiconductor integrated circuit device has a memory array which includes amplifying MOSFETs of sense amplifiers which amplify small voltages read out of dynamic memory cells onto bit lines and column switch MOSFETs which select bit lines, a read/write section which includes main amplifiers for reading out stored data from memory cells selected by the column switch, and a logic circuit which implements the input/output operation of data with the read/write section. Two capacitors each having a first electrode which corresponds to a plate electrode with the same structure as that of storage capacitors of dynamic memory cells and a second electrode which is multiple commonly-connected storage nodes of the storage capacitors are arranged in serial connection, disposed contiguously to the read/write section, and connected between operation voltage lines of the read/write section.

Semiconductor integrated circuit device having stabilizing capacitors connected between power lines of main amplifiers

A logic block of a memory (LSI) with logic functions includes RAM macrocells (RAMO-RAM7) and a centrally located gate array (GAO-GA5). Clock pulse shaping circuits (CSPO, CSP1) and input/output portion (I/O) surround the logic block. The logic block power supply includes a smoothing capacitor (CC) that is substantially the same size as a cell (GC) of the gate array. Each RAM macrocell has memory mats (MATOO-MAT21), word lines (WO-W127), data lines (DO-D7), and peripheral circuits (MPCOO-MPC21), which includes an address decoder and a sense amp (SAO). An input unit cell (ICO) receives ECL level signals and outputs ECL level signals (FIG. 5 ) and MOS level signals (FIG. 6 ). The input unit cells and analogous output unit cells (OCO) are selectively used singly or in parallel to accommodate signals of different form and driving capability. A wiring line replacement region (LRP) connects memory macrocell wiring lines with logic block wiring lines. A sequence control circuit cell or aligner (ALNO, ALN1) contiguous to the RAM macrocells transmits output signals to the logic block on the wiring lines. A clock signal distribution circuit (CDA) is arranged centrally of the RAM macrocells for distributing ECL level clock signals. The clock signal distribution circuit includes clock switch amplifier circuits (CSAO-CSA9) including bipolar transistors and MOSFETs (FIG. 23 ).

Semiconductor integrated circuit device

A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.

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Ome, Japan

Michiaki Nakayama