Intel Corporation

Michelle J Moravan

Ron Gabor

Shlomo Raikin

Ehud Cohen

Zeev Offen

Julius Yuli Mandelblat

Larisa Novakovsky

Geeyarpuram N Santhanakrishnan

A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system.

Posting weakly ordered transactions

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Haifa, Israel

Michelle J Moravan