Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Michele Taliercio

Piero Capocelli

Andrea Baroni

Rajamohan Varambally

Rinaldo Poluzzi

Gianguido Rizzotto

Vincenzo Daniele

Danilo Rimondi

Mario Lavorgna

Cosimo Torelli

Marco M Monti

Luigi Carro

Giovanni Mastrodomenico

A memory device generator for generating memory devices in a CAD environment, the generator composed of a library file containing predefined basic circuit components; memory array generation algorithm interacting with the library file for generating a variable-size memory array representation having a variable number of memory elements, and at least one redundant memory element; memory element selection circuit generation algorithm interacting with the library file for generating a memory element selection circuit to be associated with the memory array for selecting at least one memory element according to memory device address inputs. The memory element selection circuit generation algorithm having a subroutine for generating a variable-size content-addressable memory representation having a plurality of content-addressable memory locations each one associated to a respective memory element or to a redundant memory element, each of the content-addressable memory locations suitable for storing one of a set of values of the memory device address inputs and for selecting the respective memory element or redundant memory element when the memory device address inputs take the one value.

Memory device generator for generating memory devices with redundancy

A memory device comprises an array of memory cells arranged in rows and columns, a plurality of gates for transmitting respective selection outputs of a row decoder to respective rows, a dummy column of dummy memory cells substantially identical to the memory cells, precharge means for precharging the columns and the dummy column at a precharge potential when no row is selected, and programming means for setting selected columns at respective programming potentials. The device comprises dummy memory cell preset means for presetting the dummy memory cells in a first logic state when no row is selected, dummy column programming means for setting the dummy column at a prescribed programming potential corresponding to a second logic state opposite to the first logic state, and first detector means for detecting that the dummy column has discharged from the precharge potential to the prescribed programming potential and for consequently enabling said plurality of gates. Each of the gates has an input coupled to a respective dummy memory cell so that the gate is disabled as soon as the respective dummy memory cell has switched from the first logic state to the second logic state.

Memory device with reduced power dissipation

A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure, The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

High performance single port RAM generator architecture

A method for the arithmetical calculation of two-dimensional transforms including two time steps of multiplication and accumulation, of which the first step is assigned to the product of the data and of the coefficient matrices and the second step is assigned to the subsequent product by the transposed coefficient matrix. Moreover, preferably the data to be transformed and the corresponding coefficients are supplied to a first multiplication step in time succession, possibly after their storage in an appropriate memory. The device for the attainment of the method includes two multipliers with their corresponding accumulator, a random-access type memory for storing the data to be transformed and the transform coefficients, a multiplexer which receives the data first from the input and then from the memory and arranges them in a time succession for the supply to a first multiplier, and a shift register which receives the transform coefficients from the memory and arranges them for the supply to the second multiplier.

Method and device for the arithmetical calculation of two-dimensional

An integrated analog circuit having a circuit topology and intrinsic characteristics which may be selected by digital control means is formed by batteries of similar circuit components arranged substantially in parallel or in a matrix array, anyone of which may be isolated or not by means of a dedicated integrated switch and by alternative interconnection paths among the different circuit components and/or batteries of circuit components, which may be also be selected by closing a relative integrated switch. A dedicated nonvolatile memory, integrated on the same chip may be permanently programmed and determine a certain configuration of all the integrated switches thus selected a particlar component or more components of each of said batteries of functionally similar components, and/or selecting a certain interconnection path among the different circuit components in order to form a functional integrated circuit having the desired topology and intrinsic characteristics. The integrated nonvolatile memory is programmed by means of a software program which may take as input data the desired values of the different parameters which determine the intrinsic characteristics of the functional analog circuit and the type of functional analog circuit itself.

Analog integrated circuit having intrinsic topologies and

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Arluno, Italy

Michele Taliercio