Pdf Solutions, Incorporated

Michele Squicciarini

Christopher Hess

Stefano Tonello

Michele Quarantelli

Angelo Rossoni

Circuits for performing four terminal measurement point (IMP) testing of devices under test (DUT) is provided. The DUT and the circuit is to be defined on a semiconductor chip. The circuit includes a DUT having a first terminal and a second terminal, where the first terminal of the DUT is connectable to a first terminal measurement point and a third terminal measurement point, and the second terminal of the DUT is connectable to a second terminal measurement point and a fourth terminal measurement point. A first transistor is provided to select access to the first terminal measurement point, a second transistor is provided to select access to the third terminal measurement point, a third transistor is provided to select access to the second terminal measurement point; and a fourth transistor is provided to select access to the fourth terminal measurement point. In one example, the DUT is linked to neighboring DUTs, and selected ones of the first through fourth transistors are shared, thus reducing the number of transistors per DUT in a DUT bank, and reducing the area needed to implement DUT bank testing for addressable 4-IMP testing. The compact circuitry further enables DUT bank stacking in rows, addressing of columns of DUTs for conditional testing, and three dimensional stacking of DUT banks on different levels.

High density test structure array to support addressable high accuracy 4-terminal measurements

Circuits for performing four terminal measurement point (TMP) testing of devices under test (DUT) is provided. The DUT and the circuit is to be defined on a semiconductor chip. The circuit includes a DUT having a first terminal and a second terminal, where the first terminal of the DUT is connectable to a first terminal measurement point and a third terminal measurement point, and the second terminal of the DUT is connectable to a second terminal measurement point and a fourth terminal measurement point. A first transistor is provided to select access to the first terminal measurement point, a second transistor is provided to select access to the third terminal measurement point, a third transistor is provided to select access to the second terminal measurement point; and a fourth transistor is provided to select access to the fourth terminal measurement point. In one example, the DUT is linked to neighboring DUTs, and selected ones of the first through fourth transistors are shared, thus reducing the number of transistors per DUT in a DUT bank, and reducing the area needed to implement DUT bank testing for addressable 4-TMP testing. The compact circuitry further enables DUT bank stacking in rows, addressing of columns of DUTs for conditional testing, and three dimensional stacking of DUT banks on different levels.

A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.

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San Francisco, CA, United States of America

Michele Squicciarini