Pdf Solutions, Incorporated

Stmicroelectronics S.r.l.

Michele Quarantelli

Christopher Hess

Larg H Weiland

Tomasz Brozek

Marco Pasotti

Pier Luigi Rolandi

Guido De Sandre

Sharad Saxena

Giovanni Guaitini

Marco Poles

David Iezzi

Stefano Tonello

Michele Squicciarini

Angelo Rossoni

Alberto Piadena

A novel system for in-product Bias Temperature Instability (BTI) characterization that allows for characterization of transistor degradation rates is disclosed; it is self-testing and can be embedded in real products without impacting the host functionality. The test data collected during product chip testing (at Electrical Wafer Sort) can be used for identification of abnormal material and for material disposition, or to predict the chip aging rate and premature failure risk due to BTI degradation. The system can also collect the data from the real time device aging in the field, during the host chip operational lifetime. The system is equipped with local programmable power supply generation and self-test capabilities to allow concurrent operations with the host application. The Devices Under Test (DUTs) consist of standard cell-based Ring Oscillators (ROs) which have the unique capability of decoupling the BTI effects on N-type and P-type MOSFET transistors. New switching circuitry is implemented that provides for minimal delay between the stress and measurement phases, thus giving the system the capability of fully characterizing the BTI relaxation dynamic.

Embedded system to characterize BTI degradation effects in MOSFETs

A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.

Layout for DUT arrays used in semiconductor wafer testing

A sensing circuit for sensing a memory cell, the sensing circuit having a first circuit branch electrically connectable to the memory cell to receive a memory cell current, the first circuit branch having at least one first transistor that, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.

Sensing circuit for memory cells

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Noceto, Italy

Michele Quarantelli