Micron Technology Incorporated

Intel Corporation

Michele Piccardi

Xiaojiang Guo

Kalyan C Kavalipurapu

Theodore T Pekny

Shuai Xu

Qiang Tang

June Lee

Qisong Lin

Pin-Chou Chiang

Arvind Muralidharan

Vivek Venkata Kalluru

Manan Tripathi

Jung Sheng Hoei

Shigekazu Yamada

Luyen Tien Vu

Ferdinando Bedeschi

Jonathan Scott Parry

Tommaso Vali

Feng Q Pan

Kenneth William Marr

Qing Liang

Scott Anthony Stoller

Jeremy Binfet

Eric Higgins Freeman

Umberto Siciliani

Chiara Cerafogli

Marco-Domenico Tiburzi

Erwin E Yu

Jun Shen

Taehyun Kim

Joshua Daniel Tomayer

James I Esteves

Pinchou Chiang

Aaron S Yip

Chang Hua Siau

Karl David Schuh

Dheeraj Srinivasan

Daniel J Hubbard

Ali Mohammadzadeh

Agostino Macerola

Qui V Nguyen

Jae-Kwan Park

Manik Advani

Andrea Giovanni Xotta

Jaekwan Park

Kalyan Chakravarthy C Kavalipurapu

Rohitkumar Makhija

Surendranath C Eruvuru

Guido Luciano Rizzo

Yui Shimizu

Enrico Favaro

Pin-Chuo Chiang

Control logic in a memory device initiates a read operation on a memory array of the memory device and performs a calibration operation to detect a change in string resistance in the memory array. The control logic determines whether the change in string resistance is attributable to charge loss in the memory array, and responsive to determining that the change in string resistance is attributable to charge loss in the memory array, preforms the read operation using calibrated read voltage levels to read data from the memory array.

Charge loss compensation during read operations in a memory device

In a memory sub-system, causing a standby circuit associated with a memory device to enter into a low power mode. In the low power mode, causing a reference voltage to be supplied to a voltage regulator, wherein the reference voltage causes the voltage regulator to supply a standby current level to the memory device, where the standby current level is lower than a current level supplied when the memory device is in an active mode.

Low power management for sleep mode operation of a memory device

A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

Independent plane architecture in a memory device

A system and a memory device including a driver circuit, to perform first operations including driving a resistor-capacitor (RC) sensor circuit of an electronic device to a drive voltage using a representative copy of a current that drives an electronic circuit line of the electronic device. The system and memory device including the RC sensor circuit, coupled to the driver circuit, to perform second operations including determining a first sample voltage by sampling a first representative voltage generated at the RC sensor circuit, and determining a second sample voltage by sampling a second representative voltage generated at the RC sensor circuit. The ratio of the first sample voltage and the second sample voltage is indicative of an RC time constant of the electronic circuit line.

Extracting the resistor-capacitor time constant of an electronic circuit line

A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.

Microelectronic devices, and related memory devices and electronic systems

Systems and methods of dynamically calibrating memory control signals during increase of wordline voltage for memory technologies subject to charge loss are disclosed. In one aspect, an exemplary method may comprise using an internal node, such as a wordline regulator output or return feedback line or a replica of the wordline, as proxy for the local wordline voltage. In one or more further embodiments, the proxy signal may be converted to digital signal or code and even determined in the background before the signal is needed for calibration. As a function of the disclosed technology, calibration of memory control signals, such as pass voltage and wordline read-verify voltage, may be performed during increase of the wordlines voltage with no impact or penalty on read/program time.

Systems and methods for performing dynamic on-chip calibration of memory control signals

A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.

A memory device includes a memory array comprising a plurality of wordlines and a regulator circuit selectively coupled to the plurality of wordlines, wherein the regulator circuit is configured to perform a detection routine to sample a load current from a selected wordline of the plurality of wordlines and generate a measured output voltage, wherein the measured output voltage modulates with respect to the load current. The memory device further includes a comparator circuit coupled to the regulator circuit, wherein the comparator circuit is configured to generate a comparison result based on a difference between the measured output voltage and a reference voltage and a local media controller coupled to the comparator circuit, wherein the local media controller is configured to identify a presence of a defect on the selected wordline in response to the comparison result satisfying a threshold condition.

Defect detection during program verify in a memory sub-system

A microelectronic chip device includes a semiconductor substrate and multiple on-chip strain sensors (OCSSs) constructed on the substrate at various locations of the substrate. The OCSSs may each include multiple piezoresistive devices configured to sense a strain at a location of the various locations and produce a strain signal representing the strain at that location. A strain measurement circuit may also be constructed on the semiconductor substrate and configured to measure strain parameters from the strain signals produced by the OCSSs. The strain parameters represent the strains at the various location. Values of the strain parameters can be used for analysis of mechanical stress on the chip device.

Method and apparatus for on-chip stress detection

A first digitally-controlled pump voltage level is established for a charge pump coupled to a wordline of a memory device of a memory sub-system. A determination is made whether a measured digitally-controlled voltage level of the wordline and the first digitally-controlled pump voltage level satisfy a condition. In response to determining that the condition is satisfied, a signal is generated to adjust the first digitally-controlled pump voltage level to a second digitally-controlled pump voltage level.

Managing digitally-controlled charge pump operation in a memory sub-system

Devices and techniques are disclosed herein to provide a number of different bias signals to each of multiple signal lines of an array of memory cells, each bias signal having an overdrive voltage above a target voltage by a selected increment and an overdrive period, to determine settling times of each of the multiple signal lines to the target voltage for the number of different bias signals, to determine a functional compensation profile for an array of memory cells comprising a relationship between the different bias signals and the determined settling times of the multiple signal lines.

Functional signal line overdrive

A memory device including a memory die including an internally-powered thermometer to determine a first measured operating temperature value of the memory die; detect the first measured operating temperature value satisfies one of a first condition or a second condition; and generate a first signal indicating an out-of-range operating temperature of the memory die in response to one of the first condition or the second condition being satisfied by the first measured operating temperature value. The memory die also including an externally-powered thermometer to: determine a second measured operating temperature value of the memory die; detect the second measured operating temperature value satisfies one of the first condition or the second condition; and generate a second signal indicating the out-of-range operating temperature of the memory die in response to one of the first condition or the second condition being satisfied by the second measured operating temperature value.

Memory device with detection of out-of-range operating temperature

Integrated circuit devices might include a voltage regulator comprising an input and an output, a selectively activated current path connected between the input and output, and a controller configured to cause the integrated circuit device to connect the output to the input through the current path when a voltage level of the input has a first voltage level, maintain the connection of the output and the input through the current path until the voltage level of the input has a second voltage level higher than the first voltage level, isolate the output from the input through the current path after the voltage level of the input has the second voltage level, and regulate a voltage level of the output while the output is isolated from the input through the current path.

Voltage regulation

A system includes a charge pump to charge wordlines of a memory array, a pump regulator coupled including a level detector, and dynamic clock logic coupled between the level detector and an oscillator. The logic provides clock signals to the charge pump and is to perform operations including causing the oscillator to output, to the charge pump during a first time period of a recovery period of the charge pump, a first clock signal having a lower frequency than output during a time period preceding the recovery period. The operations further include causing the oscillator to output, to the charge pump during a second time period of the recovery period that follows the first time period, a second clock signal having a higher frequency than output during the time period preceding the recovery period.

Peak current reduction using dynamic clocking during charge pump recovery period

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Cupertino, CA, United States of America

Michele Piccardi