Stmicroelectronics S.r.l.

Michele Febbrarino

Fabio Enrico Carlo Disegni

Federico Goller

Maurizio Francesco Perroni

Massimo Montanaro

Dario Falanga

A non-volatile memory receives a data read request from a processing core of a plurality of processing cores. The read request is directed to a data partition of a non-volatile memory. The non-volatile memory determines whether to process the read request using read-while-write collision management. When it is determined to process the read request using read-while-write collision management, an address associated with the read request is stored in an address register of a set of registers associated with the processing core. Write operations directed to the data partition are suspended. A read operation associated with the read request is executed while the write operations are suspended and data responsive to the read operation is stored in one or more data registers of the set of registers. The data stored in the one or more data registers of the set of registers is provided to the processing core.

Data memory access collision manager, device and method

A circuit, for managing operations for accessing a flash memory on the basis of requests received from a main CPU and from an auxiliary CPU, may be configured to: associate with the main CPU, a higher access priority to the flash memory than the access priority of the auxiliary CPU; command, in the absence of further requests for accessing the flash memory, the access to the flash memory for the main or auxiliary CPU which has initiated a first access request; verify, following a receipt of a second access request, the access priority associated with this second access request; suspend one of the first or the second access request having lower priority; and authorize the other of the first or the second access request having higher priority.

Circuit and method for managing access to memory

A memory device includes a plurality of memory cells and programming circuitry configured to select a group of memory cells, receive a first data word and program memory cells of the selected group based on the data word. The memory device includes a program circuit configured to receive at least one second data word, and, for each second data word, send a program current in parallel to discriminated memory cells based on the corresponding second data word during a corresponding program phase. The memory device further includes an optimization circuit configured to generate the at least one second data word from the first data word. The number of discriminated memory cells of the second data word is maximized compatibly with a maximum predetermined limit of the total program current provided by the program circuit.

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Bagheria, Italy

Michele Febbrarino