Teranex, Inc.

Lockheed Martin Corporation

Michele D Van Dyke-Lewis

Woodrow L Meeker

Andrew P Abercrombie

David A Duncan

Ronald W Schoomaker

Harley R Myler

A method and system for analyzing and measuring image quality between two images. A series of conversions and transformations of image information are preformed to produce a single measure of quality. A YCrCb frame sequence is first converted using RGB conversion to an RGB frame sequence. The resulting RGB frame sequence is converted using spherical coordinate transform (SCT) conversion to SCT images. A Gabor filter is applied to the SCT images to produce a Gabor Feature Set, and a statistics calculation is applied to the Gabor Feature Set. The resulting Gabor Feature Set statistics are produced for both the reference frame and the frame to be compared. Quality is computed for these Gabor Feature Set statistics to produce a video quality measure. Spectral decomposition of the frames is also performable for the Gabor Feature Set, rather than the statistics calculation, allowing graphical comparison of results for the compared frames.

Method for measuring and analyzing digital video quality

An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. In one aspect, each of the processing elements includes one or more addressable storage means and other elements arranged in a pipelined architecture. The controller includes means for receiving a high level instruction, and converting each instruction into a sequence of one or more processing element microinstructions for simultaneously controlling each stage of the processing element pipeline. In doing so, the controller detects and resolves a number of resource conflicts, and automatically generates instructions for registering image operands that are skewed with respect to one another in the processing element array. In another aspect, a programmer references images via pointers to image descriptors that include the actual addresses of various bits of multi-bit data. Other features facilitate and speed up the movement of data into and out of the apparatus. &ldquo;Hit&rdquo; detection and histogram logic are also included.

Mesh connected computed

Mesh connected computer

An apparatus for processing data has a plurality of single-bit processing elements coupled together to form an m&times;n processing element array, where m is an integer number of rows and n is an integer number of columns. Each processing element has addressable storage for storing pixel data in an array format in which each addressable storage holds all of the bits associated with one pixel; and the processing element array includes a mechanism for providing direct read/write access to the addressable storage located in any addressed row of the processing element array without requiring that data be passed through other rows of the array. The apparatus also includes an addressable input/output memory for storing pixel data in a raster scan order; and pixel corner-turning logic, coupled to the input/output memory and to the processing element array, for transferring pixel data between the input/output memory and the processing element array, and for reordering bits of the pixel data being transferred so as to convert between the raster scan order and the array format.

Directly accessing local memories of array processors for improved real-time corner turning processing

Bit-serial processors quickly multiply multiple-bit operands using significantly fewer clock cycles as compared to conventional bit-serial implementations. Exemplary embodiments process groups of operand bits simultaneously to provide the significant speed increases. Advantageously, however, the exemplary embodiments utilize logic and memory architectures which are fully compatible with, and fully useful for, conventional bit-serial applications, and the embodiments thus provide fast multiple-bit multiplications while at the same time providing all of the advantages typically associated with conventional bit-serial processors.

Methods and apparatus for performing fast multiplication operations in

Methods and apparatus for quickly dividing multiple-bit operands using bit-serial processors include strategies for eliminating the number of steps required to execute conventional division operations. According to an exemplary embodiment, a conditional subtraction step, based on a quotient bit computed during a given pass, is combined with a compare step which is used to compute a next quotient bit and which, according to conventional techniques, is ordinarily computed during a subsequent pass. Additionally, exemplary embodiments provide a zero/non-zero mask for denominator bits which extend beyond a current most significant remainder bit during a given pass. As a result, not all denominator bits need be considered during every pass. Advantageously, the methods and apparatus of the invention can provide approximately a 3 to 1 speed improvement as compared to conventional techniques.

Methods and apparatus for performing fast division operations in

A format for representing floating point numbers reduces the overhead typically associated with parsing floating point numbers and thereby provides for significantly improved processing speeds, particularly for bit-serial processors. According to an exemplary single-precision embodiment, numbers are represented using a 36-bit data format. Extra bits in the representation according to the invention allow certain conditions, such as overflow/underflow and the zero-ness of a number, to be detected and asserted quickly. Other conditions, such as denormalization are subsumed into normal processing through the extension of an exponent range in the representation.

Growing community of inventors

Orlando, FL, United States of America

Michele D Van Dyke-Lewis