Stmicroelectronics S.r.l.

Michele Borgatti

Loris Giuseppe Navoni

Pier Luigi Rolandi

Pierluigi Rolandi

Marco Pasotti

Francesco Lertora

Roberto Antonio Canegallo

Roberto Pelliconi

Chantal Auricchio

Stefania Stucchi

Zsolt M Kovacs

Lorenzo Cali'

David Dozza

Christian Gazzina

Filippo Mondinelli

Flavio Gajo

Lorenzo Cali′

Francesco Sforza

Monica Besana

A protocol-based communication between a host device (e.g., MP3 player, digital camera, palmtop, etc.) and an interface (e.g., flash mass storage card) is established automatically by providing protocol-supporting facilities in the interface, each facility supporting communication with the host device based on a respective protocol, by sending a query message from the host device to the interface specifying at least one protocol for use in protocol-based communication, by searching, within the plurality of protocol-supporting facilities provided in the interface one protocol-supporting facility supporting the protocol proposed in the query message, and if such protocol-supporting facility is found within the plurality of protocol-supporting facilities provided in the interface, by setting up the protocol-based communication between the host device and the interface based on the protocol proposed in the query message issued from the host device.

Embedded protocol selection technique, related interface and computer program product

A semiconductor substrate integrated electronic circuit includes a transmitter block and a receiver block connected through a communication network (). A data signal having a transmission period is generated on a first line that is received by the receiver block. A congestion signal is generated on a second line from the receiver block to the transmitter block when a congestion event of the receiver block occurs in order to interrupt the data signal transmission. A synchro signal is generated on a third line starting from the transmitter block, this synchro signal indicating to the receiver block that the data signal comprises a new datum. The congestion signal also interrupts the synchro signal transmission when a congestion event of the receiver block occurs.

Synchronization method of data interchange of a communication network, and corresponding circuit and architecture

A system-on-chip arrangement having, in possible combination with a processor, a plurality of reconfigurable gate array devices, and a configurable Network-on-Chip connecting the gate array devices to render the arrangement scalable. The arrangement lends itself to be operated by mapping in one device of the gate array a set of processing modules, and configuring another device of the plurality of gate array devices as a microcontroller having stored therein software code portions for controlling inter-operation of the processing modules stored in the one device of the plurality. The arrangement is thus adapted, e.g., to handle different computational granularity levels.

Architecture for dynamically reconfigurable system-on-chip arrangements, related methods and computer program product

A network, such as a network on chip, includes a plurality of levels of switches organized in a hierarchy. The connections between the switches are constituted by connections which are able to transport packets of information in opposite directions in such a way that one switch, or one process associated thereto, can send or receive packets in the framework of the network along one and the same path, constituted by an ascending stretch, in which the packet goes up the network hierarchy as far as a root switch common to the source and to the destination, and a descending stretch in which the packet goes down the network hierarchy towards the destination. A routing logic is provided, configured for defining the routing path in a non-adaptive way, selecting the ascending stretch according to the source and the descending stretch according to the destination, irrespective of the traffic of the packets.

Routing procedure and system, corresponding network, such as a network on chip (NOC), and computer program product therefor

A dynamically reconfigurable processing unit includes a microprocessor, and an embedded Flash memory for non-volatile storage of code, data and bit-streams. The embedded Flash includes a field programmable gate array (FPGA) port. The reconfigurable processing unit further includes a direct memory access (DMA) channel, and an S-RAM embedded FPGA for FPGA reconfigurations. The S-RAM embedded FPGA has an FPGA programming interface connected to the FPGA port of the Flash memory through the DMA channel. The microprocessor, the embedded Flash memory, the DMA channel and the S-RAM embedded FPGA are integrated as a single chip.

Reconfigurable signal processing IC with an embedded flash memory device

An electronic system supporting modular expansion of its functions is of a type including a portable host electronic device associated with an expansion module adapted for quick-connect engagement and disengagement in/from the portable device. The expansion module includes a series of peripheral devices adapted to serve different classes of functions; a non-volatile memory storing information that pertains to configuring the different functions in the module; a re-configurable device adapted to establish connections, implement functional portions, and control all the system components; a control device adapted to cooperate with the host device in guiding the steps for re-configuring the whole system; and a software algorithm adapted to instruct the system to re-configure itself on which function and with which characteristics.

Electronic system having modular expansion function facilities

An application-specific embeddable flash memory having three content-specific I/O ports and delivering a peak read throughput of 1.2 GB/s. The memory is combined with a special automatic programming gate voltage ramp generator circuit having a programming rate of 1 Mbyte/s for non-volatile storage of code, data, and embedded FPGA bit stream configurations. The test chip uses a NOR-type 0.18 &#x3bc;m flash embedded technology with 1.8V power supply, two poly, six metal and memory cell size of 0.35 &#x3bc;m.

Embeddable flash memory system for non-volatile storage of code, data and bit-streams for embedded FPGA configurations

A nonvolatile switch has: an input terminal; an output terminal; a selection terminal; a first and a second biasing terminal; a memory element of flash type, having a first conduction region connected to the first biasing terminal and a second conduction region connected to the second biasing terminal; a pass transistor, having a first conduction region connected to the input terminal and a second conduction region connected to the output terminal; and a common floating gate region and a common control gate region, which are capacitively coupled together. The memory element and the pass transistor share the common-gate regions, and the common control gate region is connected to the selection terminal.

Nonvolatile switch, in particular for high-density nonvolatile programmable-logic devices

The invention relates to a method of expanding the functional capabilities of portable electronic devices with user friendly modes, wherein a host device is associated a quick-connect function-expanding module. In this method, at each installation of a given module, the functional expansion module and the host device recognize each other; on first installation of a given module in the host device, a series of checking operations are carried out automatically; the user can select to activate the available expansion; and once a given application is selected, the configuration and functions required for each application are stored.

Method for expanding in friendly manner the functionality of a portable electronic device and corresponding portable electronic device

The voice message managing method for a voice data recording/playing/editing electronic device, said electronic device including a memory device having a first memory area and a second memory area, includes the steps of memorizing, in the first memory area, a plurality of voice messages, and of memorizing, in the second memory area, information regarding the plurality of voice messages. The method also includes the steps of organizing the first memory area as a sequence of blocks, and of memorizing in each block a portion of voice message. The method moreover comprises the steps of defining a list (FBL) containing information on the status of the blocks and memorizing the list in a first memory sub-area of the second memory area, and of defining a table containing a plurality of first vectors associated to respective voice messages and memorizing this table in a second memory sub-area of the second memory area.

Voice message managing method, in particular for a voice data recording/playing/editing electronic device

A non-volatile memory device organized with memory cells arranged by rows and columns in a matrix structure comprising source lines for memory cell groups. A switch is set between at least two rows or columns or source lines, which has two no pilotable terminals connected respectively to each one of the two rows or columns or source lines and a pilotable terminal connected to a logic circuitry. The switch allows a precharge of one of the two rows or columns or source lines by capacitive means associated to a each one of the two rows or columns or source lines after the other of the two rows or columns or source lines is connected to a higher voltage than that of said one of the two rows or columns or source lines.

Growing community of inventors

Finale Emilia, Italy

Michele Borgatti