International Business Machines Corporation

Michel S Michail

Wilbur David Pricer

Sebastian Theodore Ventrone

Kenneth Joseph Goodnow

Clarence Rosser Ogilvie

Anthony Richard Bonaccio

James L Walsh

Janak G Patel

John Anthony Bracchitta

Steven J Tanghe

Samuel Kay Doran

Joseph R Cavaliere

John L Mauer, Iv

W David Pricer

James R Struk

Ollie C Woodard

Hannon S Yourke

Sabastian Theodore Ventrone

Janak Ghanshyambhai Patel

Drew E Albrecht

Alan K Chan

Disclosed is a system and method for eliminating the unnecessary toggling of logic in a logic network. The method and system can be incorporated directly into logic synthesis software, or may be implemented manually. Provided is a mechanism for identifying critical nets and then inserting net latches at the critical nets wherein each net latch is controlled by an enable signal that also controls a related output latch. Each net latch is comprised of a circuit which can on command hold static the last logic level on a given logic node.

Logic power optimization algorithm

A structure for an amplifier circuit which includes a pair of source-coupled differential transistors, each of source-coupled differential transistors having a body and a gate, and input transistors electrically connected to the source-coupled transistors. Also, the input transistors load the body and the gate of the source-coupled transistors with positive feedback signals. As a result, a differential gain is increased and a common mode gain is not increased. The output of the pair of source-coupled differential transistors is directed to second pair of transistors. The second pair of transistors generates mirrored voltages which track with input voltages. The second pair of transistors generates mirrored voltages translated by an offset voltage to values near ground, mirrored voltages which represent a voltage gain over an input voltage, and mirrored voltages which are largely differential and includes approximately no common mode input voltage.

Family of analog amplifier and comparator circuits with body voltage control

An apparatus and method controlling power consumption in portable personal computers by dynamically allocating power to the system logic. Expected total power consumption is calculated and compared to an optimum power efficiency value. The expected power consumption values for each execution unit are stored in a look-up table in actual or compressed form. If the expected total power consumption value exceeds the power efficiency value, selected execution units are made inactive. Conversely, if the power efficiency value exceeds the expected total power consumption value, execution unit functions are added in order to maintain a level current demand on the battery.

Apparatus and method for efficient battery utilization in portable

Disclosed is a system for providing broader bandwidth in microprocessor bus, board and system designs. Broader bandwidth is achieved by dividing the full spectrum of frequencies available into discrete bandwidth packages, much like radio communications. The system includes a bus that is controlled by a traffic controller that polls for communication requests on the bus and then allocates bandwidth among the devices submitting such requests.

Radio frequency bus for broadband microprocessor communications

A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state 'ladder' as the conditions warrant.

Self regulating temperature/performance/voltage scheme for micros (X86)

According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in a circuit by utilizing either a pull-up or pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which the circuit is inactive. By tying the circuit input high or low during inactivity, node toggling is reduced or eliminated in that circuit. In the preferred embodiment, the inputs to the circuit all pulled after a time of inactivity which is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption is minimized without excessive power loss caused by the pulling itself.

Device and method to reduce power consumption in integrated

An operational amplifier with two differential input stages is used to separately achieve low offset voltage and broad bandwidth characteristics. One input stage addresses dc and low frequency signals while the other addresses broadband frequencies. All transistors forming the dc stage are biased in the sub-threshold region. Following the two differential input stages, the signal paths are recombined in a capacitive cross-over network that provides outputs for subsequent amplification. The cross over frequency is adjustable from 15 kHz to 50 kHz using small practical values for the cross-over capacitor. The gain balance between the two input stages is adjustable by resistors and/or predetermined width/length ratios of the operational amplifier transistors.

Broadband dc amplifier technique with very low offset voltage

A soft latch circuit having a first and second inverter is disclosed. The output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter. The first inverter includes a complimentary pair of field-effect transistors (FETs). The second inverter includes either a complimentary pair of current mirrors, or a current mirror and a complimentary FET, the latter providing improved noise immunity characteristics when the soft latch is set in only one direction.

Soft latch circuit having sharp-cornered hysteresis characteristics

A matrix of thermal sensors is provided for accurately evaluating the thermal characteristics of an integrated circuit. The integrated circuit is evenly divided into a plurality of sectors in which a thermal comparison to a known thermal mass will be performed. Each sector includes at least one dual cell comprising a local thermal sensor for providing an output corresponding to a local temperature of the integrated circuit in that sector, and a background thermal sensor. The outputs of selective ones of the background thermal sensors are combined to provide a signal corresponding to a background temperature of the integrated circuit. A decoder/enabler arrangement is used to selectively gate the output of a specific local thermal sensor in a sector to a difference circuit where it is compared to the collective output of selected ones of the background sensors to generate a thermal measurement of the sector under test.

Integrated hot spot detector for design, analysis, and control

A compound cascode amplifier comprising first and second FET input transistors, the gates of which are coupled to a differential input, and first and second FET cascode transistors. The sources of the first and second cascode transistors are coupled respectively to the drains of the first and second input transistors. The gate of the first cascode transistor is coupled to a reference voltage V Ref. The drain of the first cascode transistor is coupled to the gate of the second cascode transistor, and the drain of the second cascode transistor forms the output of the circuit. In operation the drive to the gate of the second cascode transistor arrives in synchronization with the drive to the source thereof, such that the drive to the gate arrives in anticipation of a voltage swing at the output of the second cascode transistor amplifier, not in reaction to it. Accordingly, this arrangement does not introduce a delay or an additional pole in the frequency response of the circuit. A more detailed embodiment of the compound cascode amplifier further includes first and second complementary FET input transistors, and first and second complementary FET cascode transistors.

Compound cascode amplifier

A calibrated multi-voltage level system is disclosed having a network of devices, including a first and a second device. The first device comprises a processor for generating data, an encoding unit for encoding the data into a first data signal having multiple voltage levels, and a transmitting unit for transmitting the encoded data signal to the second device. The first device also comprises a calibration unit for sending a first calibration signal to the second device, and for storing a second calibration signal from the second device; and an adaptation unit for correcting the second data signal from the second device with the stored second calibration signal.

Calibrated multi-voltage level signal transmission system

A CMOS inverter circuit having a resistive bias device is disclosed. The CMOS inverter circuit comprises a pair of inverter transistors for receiving an input signal. At least one pair of compensating transistors is coupled to the inverter transistors for providing nonlinearity to the input signal. An inverter, coupled to the drains of the inverter transistors at a first node, receives the nonlinear signal as an input. The resistive bias device, coupled to the output of the inverter and to the compensation transistors, provides adjustable reference voltages to the compensation transistors, which allow for an improved noise immunity and high transition gain. The output, taken from the first node, provides for an improvement in the performance of the circuit.

Noise tolerant CMOS inverter circuit having a resistive bias

According to the preferred embodiment, a buffer amplifier is provided that provides improved linearity while providing increased control over the gain without unduly limiting the amplifier frequency response. The amplifier preferably includes a series pair of transistors with their gates connected to the amplifier input and their drains connected to the amplifier output. The amplifier further includes a pair of feedback transistors connected in series with the series pair. The gates of the feedback transistors are connected to the amplifier output through a pair of feedback networks. Each network includes at least one impedance element. The impedance elements are preferably selected to maximize the linearity of the amplifier response. Furthermore, the impedance elements can be selected to modify the gain of the amplifier, increasing the amplifier gain if needed.

Buffer amplifier with output non-linearity compensation and adjustable

An NTL (Non-Threshold Logic) NOR logic circuit exhibits a small signal swing, effected by establishing a pseudo threshold level by utilizing a low voltage power supply and a combination of NPN bipolar devices arranged to provide an essentially noise immune circuit having high DC gain and high AC noise tolerance.

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Poughkeepsie, NY, United States of America

Michel S Michail