International Business Machines Corporation

Globalfoundries Inc.

Michel Rivier

Bertrand Gabillard

Philippe Girard

Fabrice Voisin

John J Ellis-Monaghan

Phillippe Hauviller

Checking the layout integrity includes the steps of receiving inputs defining a plurality of devices for a layout, generating a signature for each device in the layout, when created, from one or more parameters of the device, storing the generated signatures with the layout, receiving the stored layout and signatures, regenerating each signature for each device in the stored layout, and comparing each regenerated signature with the corresponding stored signature.

Method of checking the layout integrity

A circuit for providing a bandgap voltage. The circuit includes a classic bandgap reference voltage generation circuit including first end second serially connected transistors acting as a current mirror to another portion of the classical bandgap reference circuit and being coupled between a supply voltage Vand an output resistor. The circuit also includes a current trimming circuit coupled in parallel with the classical bandgap reference generation circuit including a fixed element portion including a plurality of transistors and a switch portion including a plurality of switches. Each of the plurality of transistors is coupled to the supply voltage Vand to a one of the plurality of switches and each switch includes a fuse.

Bandgap reference generator utilizing a current trimming circuit

There is disclosed an improved differential amplifier () having a feedback loop that generates an amplified output signal (Vout) from an input signal (Vin) supplied by a preceding stage. It comprises an input matching circuit () connected to said preceding stage, a buffer () and an amplification section () connected in series in the direct amplification line, a first amplifier (), a RC network (') and a second amplifier () connected in series in a parallel loop between the outputs and the inputs of the amplification section that generate the feedback signal. The role of said buffer and second amplifier associated in a dedicated direct and feedback signal combining block () is to respectively isolate the input signal and the feedback signal from the summing nodes (A&#x2032;,B&#x2032;) at the amplification section inputs. As a result, the summation of the input signal and the feedback signal is improved, the DC component of the output signal is filtered out in order to significantly reduce the DC offset. In addition, the input impedance matching represented by parameter Sis considerably improved.

Differential amplifier with DC offset cancellation

There is disclosed an improved 2-stage large bandwidth amplifier () comprised of two stages formed by first and second bipolar transistors (Q,Q) configured in common emitter that are connected in series with their emitters connected to a first supply voltage (Gnd). The input signal (V) is applied to the base of said first transistor via an input terminal (), while the output signal (V) is available at an output terminal () connected to the collector of said second transistor. A parallel feedback structure (') is provided. It consists, in a first branch, of two diodes (D,D) in series connected between a second supply voltage (Vcc) and the collector of the second bipolar transistor, and in another branch of a third bipolar transistor (Q) configured in emitter follower with a resistor (Rf) in the emitter. The base and the collector of said third bipolar transistor are respectively connected to the common node of said diodes and to said second supply voltage. The resistor is connected to the common node of said first and second transistors to inject the feedback signal (V). Because, the two bodies have a low internal resistance and reduce the collector capacitance of the second transistor, the overall bandwidth of the improved amplifier is significantly extended in the very high frequencies (e.g. 20 GHz and above).

2-stage large bandwidth amplifier using diodes in the parallel feedback structure

A test circuit applicable to chips having embedded arrays intermixed with logic is described. Depending on a control signal, the test circuit connects or isolates the arrays to and from the logic. The test circuit operates as a switch placed between the power supply rail of the logic and the power supply rail of the arrays. All input gates are cross-connected to the power supply rail of the logic, and each output gate is connected to the corresponding power supply rail of the arrays. During TEST mode, the control signal turns off the test circuit, cutting off the arrays. The logic is tested while the memory cells remain unselected. Faulty chips are rejected. When the value of the control signal is inverted, a control gate connects all the power supply rails of the arrays to the power supply rail of the logic. The test sequence for the embedded array is then applied. Faulty memory cells are replaced with repairable ones; otherwise, the faulty chips are rejected. Thus, the manufacturing yield of the mixed chips is improved.

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Barbizon, France

Michel Rivier