Lucent Technologies Inc.

Agere Systems Guardian Corp.

Agere Systems Inc.

Michel Ranjit Frei

Ya-Hong Xie

Kwok K Ng

Clifford Alan King

Nathan R Belk

Yi Ma

William Thomas Cochran

Marco Mastrapasqua

Shahriar Moinian

Mark Richard Pinto

Harry T Weston

Thi-Hong-Ha Vuong

David Clayton Goldthorp

A heterojunction bipolar transistor includes an emitter or collector region of doped silicon, a base region including silicon-germanium, and a spacer. The emitter or collector region form a heterojunction with the base region. The spacer is positioned to electrically insulate the emitter or collector region from an external region. The spacer includes a silicon dioxide layer physically interposed between the emitter or collector region and the remainder of the spacer.

Heterojunction bipolar transistor

An integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.

Inductor or low loss interconnect and a method of manufacturing an inductor or low loss interconnect in an integrated circuit

Metalization structures are modeled by employing automatic substrate grounding and shielding generation in conjunction with a design and simulation process for modeling the charge distributions and the interactions of these charge distributions on metalization structures arising from voltages and currents flowing in metalization structures. By generating and, then, employing a grounding structure that is optimized to strongly screen the metalization structure being designed and simulated, the requirement is eliminated for the accurate incorporation of the strongly dependent long range metalization sub unit to sub unit charge distribution coupling from the charge distribution determination process. In one embodiment of the invention, representative metalization sub units are selected, such as straight sections of infinitesimal length, right angle bends and intersections. Charge distributions are determined in those representative sub units based on the assumption that the integrated circuit substrate strongly suppresses any long range circuit interactions or frequency dependent effects. Then, based on the above assumption, self and mutual interactions are determined of the metalization sub units. Further, based on determined characteristics of those sub units, substrate grounding structures are determined and constructed that ensure the validity of the simulation assumption that the substrate grounding is adequate to strongly suppress any long range circuit interactions and/or frequency dependent effects. The determined self and mutual interactions can then be used as initial solutions to describe all interactions between similar metalization sub units in the overall physical metalization structure to be fabricated.

Method and apparatus for modeling electromagnetic interactions in electrical circuit metalizations to simulate their electrical characteristics

A process for device fabrication in which transient enhanced diffusion (TED) is used to obtain a desired distribution of dopants in a crystalline substrate is disclosed. In the process, at least two dopants and a non-dopant are introduced into the same region of a substrate. The diffusion of the dopants in the substrate during a subsequent thermal anneal is affected by the non-dopant. The amount of non-dopant introduced into the substrate is selected to obtain, in conjunction with the subsequent thermal anneal, the desired distribution of dopants in the substrate. The concentration of the non-dopant is in the range of about 6.times.10.sup.16 atoms/cm.sup.3 to about 3.times.10.sup.21 atoms/cm.sup.3. The substrate is then annealed at a temperature in the range of about 700.degree. C. to about 950.degree. C. to obtain the desired dopant profile.

Process utilizing selective TED effect when forming devices with shallow

A wafer configured for in-process electrical testing is disclosed. According to the invention, a single RF-device monitor is disposed partially in a first street and partially in a second street orthogonal to the first street, between four adjacent dies present on a wafer. With such an arrangement, streets having a width of 100 microns and less are suitable for accomodating a RF-device monitor having a ground-signal configuration. As a result, less space is sacrificed for device monitors than in prior art wafers, thereby increasing the amount of wafer area available for circuitry.

Article and method for in-process testing of RF products

A device with at least one noise-sensitive element, at least one noise-generating element, and a porous silicon barrier in the substrate is disclosed. The porous silicon barrier isolates the noise-sensitive element from the signals coupled into the substrate by the noise-generating element. A process for making this device is also disclosed.

Growing community of inventors

Berkeley Heights, NJ, United States of America

Michel Ranjit Frei