International Business Machines Corporation

Michel Poret

Alain R Blanc

Rene J Glaise

Francois Le Maut

Rene Gallezot

Claude Basso

Natarajan Vaidhyanathan

Joseph Allen Kirscht

Alan Frederic Benner

Francois Abel

Todd Alan Greenfield

Ethan M Spiegel

Mitch Gusat

Norbert Schumacher

Jean-Marie L Munier

Bernard Brezzo

Sylvie Gohl

Mark Verhappen

Jean-Claude Robbe

Daniel Wind

Ronald Pete Luijten

Jean-Claude Abbiate

Gerard Orengo

Maurice Cukier

Alain Saurel

Pierre Austruy

Michel Colmant

Jean M Munier

Jocelyne Jaumes

Laurent Nicolas

Michael Colmant

Christian Landry

Michael Peyronnenc

René Glaise

Embodiments presented herein describe techniques for isolating multicast and broadcast frames to a traffic class that is separate from a traffic class used for unicast frames. According to one embodiment, a network switch receives an incoming Ethernet virtual local area network (VLAN)-tagged frame. The switch evaluates priority bits of the VLAN tag of the frame. The switch also determines a type of frame (e.g., whether the frame is unicast, broadcast, multicast, or flood). Based on the priority field values and the type of the frame, the switch identifies a mapping of the frame to a particular traffic class. The network switch assigns the frame to the traffic class.

Unified framework for isolating multicast and broadcast frames to a traffic class separate from a traffic class used for unicast frames

Embodiments presented herein describe techniques for parsing an Internet Protocol version 6 frame and skipping extension headers of the frame. A configurable skip list is provided that specifies extension headers for a networking device to skip when parsing the frame. The networking device examines 'next header' fields of each extension header to determine a next extension header in the chain. If the next extension header matches an extension header in the skip list, the networking device iterates to the next header in the chain until the end of the chain (or an extension header that does not contain a match in the list) is reached.

Skipping and parsing internet protocol version 6 (IPv6) extension headers to reach upper layer headers

Skipping and parsing internet protocol version 6 extension headers to reach upper layer headers

In a network device packets are marked with sequence identifiers at ingress of the device, switched through a plurality of switching planes and re-sequenced on a per flow basis at egress of the device. The re-sequencing system includes a controller that allocates to each received data packet a temporary storage location in a packet buffer. A plurality of output registers are provided, with each one associated with a flow. A pointer uses predefined parameters to point to an output register that has been previously assigned to receive data packets from the corresponding flow. Parameters in the pointed output register are correlated with parameters in a received packet to determine if the received packet is next in sequence to packets processed through a particular queue.

System and method for re-sequencing data packets on a per-flow basis

A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism is disclosed. An egress location for an ingress port is selected based on degrees of freedom for the selection mechanism. The degree of freedom can be derived from the collapsed virtual output queuing array by determining a number of egress locations to which an ingress port may send packets and determining a number of ingress ports from which an egress location can receive packets. Analyzing all the queued packets for assignment to an egress location, starting with a lesser degree of freedom and ending with a greater degree of freedom provides efficient switching allocations and acknowledgements.

Algorithm and system for selecting acknowledgments from an array of collapsed VOQ's

A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects being handled, while providing desirable signal characteristics such as signal DC balance and enough signal transitions. The overhead introduced by the method is a modest increase over the original overhead of the 10 Gb Ethernet 64B/66B code.

Forward error correction scheme compatible with the bit error spreading of a scrambler

A communication system which consists of several modules&#x2014;operating in parallel on segments of a packet&#x2014;to increase speed and handling capacity. One module acts as master, the others are slave modules controlled by control signals derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.

Method and arrangement for local sychronization in master-slave distributed communication systems

A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets 'WPC' temporarily stored within an egress buffer to a predefined threshold value 'WPCth'. The packet sequence number &#x2018;PSNr&#x2019; of a last received in-sequence data packet and each highest packet sequence number &#x2018;HPSNj&#x2019; received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number &#x2018;PSNr&#x2019; to each highest packet sequence number &#x2018;HPSNj&#x2019; when the number of data packets &#x2018;WPC&#x2019; exceeds the predefined threshold value &#x2018;WPCth&#x2019; a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.

Packet unstopper system for a parallel packet switch

An embodiment of the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter has a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location, a controller, and a determination means coupled to a storing means and extracting means.

CAM based system and method for re-sequencing data packets

A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.

Data packet switch and method of operating same

For switching or transmitting data packets, one can provide communication systems which consist of several modules &#x2014;operating in parallel on segments of a packet &#x2014;to increase speed and handling capacity. One module acts as master, others are slave modules controlled by control signals derived by the master module. It is important to correctly synchronize in each module the data segment and the respective control signal of each packet, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.

Method and arrangement for local synchronization in master-slave distributed communication systems

A system and a method to avoid packet traffic congestion in a shared-memory switch core, while dramatically reducing the amount of shared memory in the switch core and the associated egress buffers, is disclosed. According to the invention, the virtual output queuing (VOQ) of all ingress adapters of a packet switch fabric are collapsed into its central switch core to allow an efficient flow control. The transmission of packets from an ingress buffer to the switch core is subject to a mechanism of request/acknowledgment. Therefore, a packet is transmitted from a virtual output queue to the shared-memory switch core only if the switch core can actually forward it to the corresponding egress buffer. A token based mechanism allows the switch core to determine the egress buffer's level of occupation. Therefore, since the switch core knows the states of the input and output adapters, it is able to optimize packet switching and to avoid packet congestion. Furthermore, since a packet is admitted in the switch core only if it can be transmitted to the corresponding egress buffer, the shared memory is reduced.

System and method for collapsing VOQ's of a packet switch fabric

A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism. According to the method, an efficient set of virtual output queues (at most one virtual output queue per ingress adapter) is selected, while keeping the algorithm simple enough to allow its implementation in fast state machines. For determining a set of virtual output queues that are each authorized to send a packet, the algorithm is based upon degrees of freedom characterizing states of ingress and egress adapters. For example, the degree of freedom, derived from the collapsed virtual output queuing array, could represent the number of egress ports to which an ingress port may send packet, or the number of ingress ports from which an egress port may receive packets, at a given time. Analyzing all the ingress ports holding at least one data packet, from the lesser degree of freedom to the greater degree of freedom, the algorithm determines as many virtual output queues as possible, in the limit of the number of ingress ports (an ingress port may send only one packet per packet-cycle).

A method and a system to adapt the load balancing of the incoming traffic over the planes of a parallel packet switch (PPS) on the basis of the monitoring of requests and acknowledgments exchanged between ingress port adapters and arrays of collapsed virtual output queues (cVOQ) situated within the plane switch cores is disclosed. According to the invention, at least one counter is associated, in each ingress port-adapter, to each individual switching plane or device to be monitored. Each of these counters is incremented when a request is sent to the corresponding individual switching plane or device and decremented when an acknowledgment is received from this individual switching plane or device. When the range of values taken by the counters of a same ingress port-adapter reaches a predetermined threshold, less (or none) incoming traffic is further transmitted to the individual switching plane or device associated to the higher value counter. An alarm signal is possibly raised too e.g., for replacing the defective individual switching plane or device.

Growing community of inventors

Gattieres, France

Michel Poret