International Business Machines Corporation

International Business Corporation

Michel Paul Verhaeghe

Patrick Michel

Jean-Francois Le Pennec

Alain Benayoun

Gerard Orengo

Philippe Pierre Louis

Jean-Claude Froment

Claude Gomez

Philippe Hauviller

Philippe Klein

Jean-Pierre Pantani

Jacques Feraud

Jean-Louis H Marijon

Christian Ouazana

Bernard Sergent

Gerard Jean-Marie Delarue

Automatic speed adaptation system in a Local Area Network (LAN) between a hub ( ) including a hub adapter ( ) and at least a workstation ( ) including a workstation adapter ( ) for exchanging data over a link connected between the hub adapter and the workstation adapter at a rate based on a frequency which is inversely proportional to the length of the link. Each adapter comprises a clock generator for generating a clock having a frequency between F and F and processing means for transmitting at least a check frame from the hub adapter to the workstation adapter at a rate based on a frequency VCLK generated by the clock generator under the control of the processing means and selected as being the frequency corresponding to the length of the link, and for transmitting an acknowledge frame from the workstation adapter to the hub adapter thereby ascertaining that the selected frequency is the right frequency resulting in the best quality of transmission.

Automatic rate adaptation system in a local area network

Method and system for wide band decoupling of integrated circuits

Method for reducing the effects of signal reflections in a data communications network

A memory statistic counter and method for counting the number of accesses (writes or reads) by a microprocessor ( ) to at least a portion of a memory comprising a decoding logic unit ( ) for providing a selection signal for selecting the portion of memory in response to control signals from the microprocessor, and adding logic units ( ). The memory statistic counter includes a register which is incremented each time the portion of memory is accessed by the microprocessor and providing a registration signal when the number of accesses is equal to a predetermined number, and a queuing unit ( ) for registering a value in a registering memory ( ), such as a first-in-first-out (FIFO) memory, in response to the registration signal and providing an interrupt signal to the microprocessor when all locations of the registering memory have been filled, thereby indicating to the microprocessor that a defined number of accesses to the portion of memory has occurred.

Memory statistics counter and method for counting the number of accesses to a portion of memory

Device for cancelling the effects of the reflection in a signal transmission system ( ) including a driver ( ) and a plurality of n receivers ( ) wherein signals are sent according to a multipoint topology from the driver to the receivers, each receiver having an internal capacitance and sending back reflection signals to the driver each time a signal is transmitted thereto by the driver. The device comprises circuit means causing the signal resulting from the sequential reflections due to a given receiver and then due to the driver to have the same magnitude but the reverse sign as the sum of all signals received in the given receiver resulting from the reflections due to all receivers, and the net linking the driver to each receiver comprises delay means ( ) enabling the propagating time of a signal sent from the driver to this receiver to be identical for each receiver, whereby the total sum of all reflection signals arriving in the given receiver at the same time is equal to zero.

Device for cancelling the reflection effects between a driver and a plurality of receivers

A method and apparatus for distribution of electrical signals in a circuit board. Specifically, the circuit board comprises a printed circuit board and a plurality of connectors attached to the circuit board for receiving components such as logic cards which each require a clock input. Each of the connectors may have a plurality of pins. A plurality of electrical conductors associated with the circuit board electrically couple a corresponding pin for a clock input from each connector to a common point by individual one of the plurality of electrical conductors. Each of the plurality of electrical conductors are so arranged that to have approximately the same length.

High speed signals distribution for backplanes

Printed circuit board comprising two power supplies V.sub.1 and V.sub.2 and a ground (GND), and a plurality of modules among which at least one module supplied by one of the power supplies can be replaced by another pin-compatible module supplied by the other power supply, each power supply being supplied in each case by a circuit including a ferrite connected to the power supply and a capacitor connected to the ground in order to filter the high frequency signals due to the switching operations in the modules. The board comprises a first area (24 or 24') having a first and a second terminals which is dedicated to a first ferrite to be connected to one power supply by means of its first terminal, and a second area (26 or 26') having a first and a second terminals and being dedicated to a second ferrite to be connected to the other power supply by means of its first terminal, each area including a connecting means for connecting the second terminal associated with the area to the footprints of the module.

Printed circuit board allowing usage of alternative pin-compatible

A device implemented in a N-bit digital-to-analog converter (DAC) to extend its resolution to N+P bits. The N-bit DAC comprises a resistive string 2 made of 2.sup.N resistive elements R1 to R16. MSB switches in block 10 and LSB switches in block 12, when closed in response to combinations of the N-bits provide the voltage at one of taps N1 to N16 to node M1. The device comprises a string 18 made of 2.sup.P-2 elements connected between nodes M1 and M7, additional LSB switch block 14 and additional MSB switches SW4-2, SW8-2, SW12-2 and SW16-2 which are closed in response to combinations of the N-bits to connect the string 18 across the taps of a selected resistor R1 to R16. The voltage generated at one of the taps M1 to M7 of string 18 is provided to the (N+P)-bit DAC output 20 by means of one of the switches in block 16. The main advantages of this device are that the monotonicity of the conversion is not impaired by the extension to (N+P) bits, and that it is not space consuming when integrated in a chip. Furthermore, various conversion capabilities may be provided by controlling the switch SW21 and the switches in block 16.

Device for extending the resolution of a N-bit resistive

A monolithic module acting as the interface between a modem and leased ('LL') or switched ('SL') telephone lines, mainly characterized in that: 1. It can be formed on a silicon chip (due to the absence of electromechanical relays or similar switching means), and 2. Its architecture is such that it makes it possible, by interconnecting or 'stacking' identical modules, not only to attach additional telephone lines, but also to increase the number of allowable modem configurations. The module (10, 10') comprises two controlled-type line amplifiers (DLL, DSL) which exhibit a high output impedance regardless of whether the power supplies are 'on' or 'off'; two controlled-type line receivers (RSL, RLL) which provide a very high input impedance whether the power supplies are 'on' or 'off'; and a wrap receiver (WRP) for testing the modem (to the exclusion of the telephone lines) and interconnecting or 'stacking' identical modules. The figure shows an embodiment wherein two of the modules are interconnected; various configurations can be obtained depending on the logic state of the control inputs (1 to 4 for module 10 and 1' to 4' for module 10') supplied by the modem.

Interface module for telephone lines

A voltage comparator circuit with a wide common mode input voltage range which extends beyond supply voltage parameter values. The comparator circuit utilizes an input stage having two input transistors, the emitter electrodes of which are connected to receive input signals and the collector electrodes of which are connected to two current sources. A current fixing circuit is coupled to the collector electrodes of said two input transistors and acts to fix the direct current in the collector circuits at a first value IO and the currents supplied by the current sources at a second value k IO, where k is greater than 2. An output stage is provided with two input circuits respectively connected to the collector electrodes of the two input transistors and with a logic circuit arrangement set to either one of two logic levels in accordance with the sign of the difference in the voltages applied to the pair of emitter electrodes of the two input transistors.

Voltage comparator with a wide common mode input voltage range

A digital signal distribution system for distributing digital signals to remote points of a machine. It is comprised of a distribution device arranged at each of said points. In each device, a receiver receives on its true and complementary inputs, the signal to be distributed. The drivers are connected to the receivers through a crossed connection, the true output of the receiver being connected to the complementary input of the driver, and the complementary output of the receiver being connected to the true input of the driver, so as to cancel the skew of the pulse width of the signal to be distributed. The signals on outputs of the driver circuits can be utilized locally or transmitted to another remote point.

Digital signal distribution system

An improved wideband frequency multiplier characterized as follows: a saw-tooth signal generator supplying a saw-tooth wave having a frequency equal to the frequency to be multiplied, the level of the voltage wave varying between a reference level and a maximum which is related to the frequency to be multiplied; storage means for storing a voltage equal to, or closely approaching the maximum voltage value of the saw-tooth wave; a voltage divider having several outputs, each of which provides an output which is a given fraction of the stored voltage; a number of comparators each of which corresponds to and is coupled to an output of the voltage divider, each comparator comparing the instantaneous value of the saw-tooth voltage with the voltage supplied by the corresponding output of the voltage divider, and supplying a first level signal when said instantaneous value is lower than the voltage supplied by said corresponding output, and a second level signal when it is higher; and logical circuits combining the signals supplied by the comparators so as to give an output signal the frequency of which is a given multiple of the frequency of the saw-tooth signal. A timing circuit for a badge reader, or the like where the data is magnetically NRZ recorded on, or in, the badge, or the like. The timing circuit employs a frequency doubler as generally described above. The timing circuit also utilizes at least one additional logic circuit. The timing circuit provides timing signals synchronized with the reading of the data from the badge or the like.

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Cagnes sur Mer, France

Michel Paul Verhaeghe