Synopsys, Inc.

Michel Luc Cote

Christophe Pierrat

Michael Lawrence Rieger

Robert M Lugg

Philippe Hurat

Jeff Mayhew

Definition of a phase shifting layout from an original layout can be time consuming. If the original layout is divided into useful groups, i.e. clusters that can be independently processed, then the phase shifting process can be performed more rapidly. If the shapes on the layout are enlarged, then the overlapping shapes can be grouped together to identify shapes that should be processed together. For large layouts, growing and grouping the shapes can be time consuming. Therefore, an approach that uses bins can speed up the clustering process, thereby allowing the phase shifting to be performed in parallel on multiple computers. Additional efficiencies result if identical clusters are identified and processing time saved so that repeated clusters of shapes only undergo the computationally expensive phase shifter placement and assignment process a single time.

Handling of flat data for phase processing including growing shapes within bins to identify clusters

A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.

Layout of phase shifting photolithographic masks with refined shifter shapes

Design-specific attributes of a circuit (such as timing, power, electro-migration, and signal integrity) are used to automatically identify one or more regions of one or more layers in a layout of the circuit. The automatically identified regions may be provided to a manufacturing tool in GDSII by use of overlapping shapes in, or alternatively by moving existing shapes to, a different layer/datatype pair. For example, information about the automatically identified regions may be stored using a conventional datatype (e.g. value) with a new layer, or alternatively using a conventional layer (e.g. metal) with a new datatype (e.g. value), depending on the embodiment. The automatically identified regions contain cells and/or features (e.g. groups of shapes and/or individual shapes) whose tolerance in silicon (to be fabricated) is automatically changed from default, based on the design-specific attribute(s) and sensitivity thereto, expressed as design intent by a circuit designer.

Silicon tolerance specification using shapes as design intent markers

Design and layout of phase shifting photolithographic masks

Mask and integrated circuit fabrication approaches are described to facilitate use of so called 'full phase' masks. This facilitates use of masks where substantially all of a layout is defined using phase shifting. In one embodiment, the phase shifting mask and the trim mask are exposed using substantially the same exposure conditions. These approaches facilitate better exposure profiles for the resulting ICs and can thus improve chip yield and increase throughput by reducing the need to alter settings and/or switch reticles between exposures.

Exposure control for phase shifting photolithographic masks

Design-specific attributes of a circuit (such as timing, power, electro-migration, and signal integrity) are used to automatically identify one or more regions of one or more layers in a layout of the circuit. The automatically identified regions may be provided to a manufacturing tool in GDSII by use of overlapping shapes in, or alternatively by moving existing shapes to, a different layer/datatype pair. For example, information about the automatically identified regions may be stored using a conventional datatype (e.g. value 0) with a new layer, or alternatively using a conventional layer (e.g. metal 3) with a new datatype (e.g. value 1), depending on the embodiment. The automatically identified regions contain cells and/or features (e.g. groups of shapes and/or individual shapes) whose tolerance in silicon (to be fabricated) is automatically changed from default, based on the design-specific attribute(s) and sensitivity thereto, expressed as design intent by a circuit designer.

Mask and integrated circuit fabrication approaches are described to facilitate use of masks where substantially all of a layout is defined using phase shifting. Exposure settings including relative dosing between the phase shift mask and the trim masks are described. Additionally, single reticle approaches for accommodating both masks are considered. In one embodiment, the phase shifting mask and the trim mask are exposed using the same exposure conditions that have an effect on the characteristics of the radiation used for the exposure, except for relative dosing. The same exposure conditions are changeable optical parameters that consist of numerical aperture (N.A.), wavelength (&#x3bb;) of radiation, partial coherency (&#x3c3;), illumination configuration, and defocus. These approaches facilitate better exposure profiles for the resulting ICs and can thus improve chip yield and increase throughput by reducing the need to alter settings and/or switch reticles between exposures.

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San Jose, CA, United States of America

Michel Luc Cote