Alcatel Thomson Faisceaux Hertziens

Michel Le Calvez

Michel Peruyero

A circuit for delaying at least one high bit rate data train, the circuit comprising: first (25) and second (26) first-in-first-out (FIFO) type registers having 'm' inputs and 'n' words in series; a binary counter (27) delivering a most significant bit signal (MSB); a write/read control circuit (28) for controlling writing and reading in said register (25, 26) and comprising: a circuit for switching a clock signal (H) alternatively to each of the two registers (25, 26) in order to write in one of the two registers while simultaneously reading from the other, and vice versa; a circuit (33, 34) for dynamically resetting said registers (25, 26) to zero immediately prior to each write stage; and a circuit (35) for generating an output enable signal for controlling said registers to enable the previously input data to be output therefrom after a delay of 'n' clock periods since the beginning of a write stage.

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Boulogne Billancourt, France

Michel Le Calvez