International Business Machines Corporation

Michel L Costes

Alain R Gach

Kenneth James Barker

Michel H Peyronnenc

Yves Hartmann

Gerard Dalboussiere

Francis E Baudelot

Gerard M Montanari

Gene D Hodge

Jean-Pierre C Dugre

An adapter No (n-1) propagates a daisy-chained grant signal directly to the adapter No (n) and a by-passed grant signal to the adapter No (n+1) case. The adapter No (n) is responsive to the status of the previous adapter in the chain, for determining which of the regular grant signal ('GR') or by-passed grant signal ('GRA') has to be taken account of by the succeeding adapter, when the latter wants to access the transmission bus (11). Further, the adapters connected to the chain may be partitioned into groups (80) within which the grant signal is distributed in parallel to the adapters, and propagated to the next group only when none of its adapters (10) requests access to the transmission bus. The same priority level is given to each adapter or group of adapters connected to the daisy-chain, and permits said chain to remain operative even when several adapters are unplugged or malfunction.

System for selectively detecting and bypassing inoperative module within

An interface mechanism is described for controlling the exchange of information between two devices, such as a direct memory access controller 12 and adapter 5 through bus 10. The exchange is initiated by the adapter which activates the request line 44 and read/write signal on line 62 indicating whether a memory read or write operation is requested. The controller sends back a grant signal on line 46 when the request may be serviced. Ready line 60 is monitored and checked by the adapter and valid line 52 is monitored and checked by the controller. Turn around signal on line 64 controls the direction of the transfer on bidirectional data lines 66. A write or read operation begins with the transmission by the adapter of control parameters (address and byte count). Then for a write operation, the data burst is sent from the adapter to the controller and for a read operation the data burst is sent from the controller to the adapter. The sampling clock always travels with the parameters and data. Controller 12 transmits data with a clock 28 used by the adapter to sample that data and adapter transmits data with a clock 36 used by the controller 12 to sample that data. Clock 36 is generated by inverting clock 28. Thus the bus presents the advantages of synchronous and asychronous modes of operation. The data exchanges are synchronous, so that no time is wasted in handshaking protocols. Because of its asynchronous nature between transfers, the bus is independent of the controller data handling scheme, memory type and memory access time.

System with plural clocks for bidirectional information exchange between

The high speed line adapter comprises a bit handling layer (34,46) and a byte handling layer (36,50) and a receive queue mechanism (48). The bit layer receives the frames from the high speed line 9. It performs the SDLC protocol, it removes the flag and BCC characters and adds one ending condition control character which indicates whether the frame was correctly received or not. It causes the address and control fields, the data if any and the ending condition character to be stored into a receive queue buffer at the first free address. The byte layer 50 takes out the frame characters from the receive queue as soon as a pool buffer is available in the memory of the central unit of the communication controller. It sends the data if any to said memory through a direct access memory bus and sends the address and control fields and the ending condition to the microprocessor of the adapter. The provision of the receive queue mechanism allows high speed lines to be connected to a communication controller, without modifying its network control program.

Very high speed line adapter for a communication controller

In a data communication system, a device for performing a wrap test on at least one line without affecting the other lines that transmit and receive data over at least one multiplex link (4) within time slots allocated to a given line within a given frame. During each time slot, a wrap control bit (W) is set by the communication system to a state that indicates either the wrap test mode or the normal mode of operation. Said bit controls a logic circuit (51) to cause data to be sent either over line (4) or to the receive circuit to perform the test, within each time slot.

Device for performing wrap tests on a multiplex link in a data

The disclosed circuit employs a single programmable timer and address decoder which identifies a plurality of bursts received from other stations in a TDMA communications network by means by identifying their origin addresses, and then starts associated timing intervals in the programmable timer for each burst. The instant when the intervals being timed terminate, corresponds approximately to the instant at which the local station should commence its transmission burst. The programmable timer and synchronizer associates each of a plurality of timing intervals with each of the plurality of transmitting stations in the TDMA network, and terminates each respective interval at approximately the same instant in a given local station, thus allowing the time for commencement of the local station's transmission burst to be reliably determined without regard for the participation of any more than one other of the plurality of transmitting stations in the TDMA network. This enables a TDMA communications system to be democratically synchronized in a reliable manner.

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Cagnes,Mer, France

Michel L Costes