Avaya Inc.

Michel Ivgi

Michael German

Itai Ephraim Zilbershtein

Dan Gluskin

Roee Elizov

Shlomo Davidson

Yosef Goldberg

Yair Khayat

Disclosed is a method and tool that performs glass-to-glass testing of a test AV system. The test AV system may be a transmitter device that senses AV stimuli and transmits an AV signal to a receiver device that displays video and provides an audio out/speaker of the audio. A light source and a sound source may be placed at the transmitter device. A light sensor and microphone/direct audio out connection may be placed at the receiver device. The automatic test tool may cycle synchronized light/sound stimuli to the transmitter device and measure the delay/latency times for audio, video, and AV synchronization at the receiver device. The automatic test tool may be comprised of a computer running user interface/test management software connected to a low cost FPGA that controls the video/sound sources and sensors to accurately measure both video and audio glass-to-glass latency/synchronization in a continuous, automatic, and self-calibrating manner.

Automatic glass-to-glass video and A/V sync test tool

A device including a PLD with at least one interface logic block connection for passing data between (i) a bus arranged for receiving data from an external processor and (ii) at least one I/O register connected with a JTAG interface of the PLD, wherein said interface logic block includes logic for translating data on the bus into a data format for the I/O register. A processor programmable PLD appliance comprising (a) a programmable PLD having a JTAG programming interface supporting real-time re-programming of the PLD while the PLD functions as programmed; and (b) an I/O register interfacing an I/O register and connected with the JTAG programming interface, wherein a PLD logic design implementation of the I/O register is externally accessible through an interface logic block of the PLD, and wherein the interface logic block includes a PLD path between (i) an external processor interface and (ii) the PLD-implemented I/O register.

Processor programmable PLD device

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Yehud, Israel

Michel Ivgi