Sgs-thomson Microelectronics S.a.

Stmicroelectronics S.a.

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Kalray

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Commissariat a L'energie Atomique

Michel Harrand

Elisa Vianello

Olivier Thomas

Gabriel Molas

Bastien Giraud

Yves Durand

Joseph Bulone

Olivier Deygas

Michel Runtz

Richard Ferrant

Andrew Cofler

Vincent David

Thierry Collette

Nicolas Ventroux

Benoit Dupont De Dinechin

Raphaël David

Patrice Couvert

Benoît Dupont De Dinechin

Stéphane Louise

Jean-Marc Daveau

Frédéric Blanc

José Sanches

Thierry Lepley

Gilles Eyzat

Thomas Champseix

Paul Mougeat

Michel Henry, Deceased

David Boise

Claire Henry

Pierre Paulin

Philippe Guillaume

Miguel Santana

Marco Cornero

Christian Freund

Denis Dutoit

François Druilhe

Cécile Nail

The invention relates to a resistive memory () including resistive elements, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, the memory further comprising a device () for switching the resistance of at least one resistive element selected from among the resistive elements between the high and low values, the device including a first circuit capable of applying an increasing voltage across the selected resistive element while the selected resistive element is at the high value or at the low value, a second circuit capable of detecting the switching of the resistance of the selected resistive element, and a third circuit capable of interrupting the current flowing through the selected resistive element on detection of the switching.

Device and method for writing data to a resistive memory

A system including: a first memory including several portions each of several pages, this memory including first and second ports that enable simultaneous access to two pages of distinct portions of the memory; and a control circuit suitable for implementing, via the second port, a method for balancing the wear of the memory, including movements of data within the memory, while authorizing simultaneous user access to the memory contents via the first port.

System for managing the wear of an electronic memory

A method for managing the endurance of a non-volatile rewritable memory including a dielectric material layer that switches between a high resistance state, with a first resistance value, and a low resistance state, with a second resistance value, the method including at least one of the following operations: at the end of each erasure operation: reading the first resistance value and comparing it with a first predetermined median resistance value, and determining the writing programming conditions from the comparison results; and at the end of each writing operation: reading the second resistance value and comparing it with a second predetermined median resistance value, and determining the erasure programming conditions from the comparison results, linking the programming conditions and the first and second read resistance values, the writing and erasure programming conditions being applied to the electrodes of the stack during the following writing and/or erasure operations.

Method for managing the endurance of a non-volatile rewritable memory and device for programming such a memory

A method for managing the endurance of a non-volatile rewritable memory including memory cells each including an ordered stack of a lower electrode, a layer of dielectric material and an upper electrode, the dielectric material switching between a high resistance state and a low resistance state, or vice versa, to enable a writing in the memory cell or an erasure of the memory cell. The method includes at the end of each writing and erasure cycle, reading the erasure conditions of the memory cell in the course of the final erasure operation of the cycle, and comparing the read erasure conditions with a predetermined median erasure value corresponding to a median resistance value which follows a predetermined dependency law linking the condition of erasure of a cycle with the condition of writing of a following cycle; and determining the writing conditions from the results of the comparison.

A system including: a memory including a plurality of pages; and a control circuit suitable for delivering user access to the memory and for implementing a balancing method for the wear of the memory, including movement of data within the memory, in which the control circuit is suitable for delivering, between the first and second consecutive page read or write operations of the wear balancing method and between the second and a third consecutive page read or write operation of the wear balancing method, one or more user accesses to the pages of the memory.

System and method for managing wear of an electronic memory

A credit-based data flow control method between a consumer device and a producer device. The method includes the steps of decrementing a credit counter for each transmission of a sequence of data by the producer device, arresting data transmission when the credit counter reaches zero, sending a credit each time the consumer device has consumed a data sequence and incrementing the credit counter upon receipt of each credit.

Stream management in an on-chip network

A system including: a first memory including several portions of one or more pages each, said memory including first and second ports that can simultaneously access, for reading and writing respectively, two distinct pages of portions of the memory; and a control circuit capable of performing write operations to the pages of the memory, each write operation to a page of the memory requiring a reading step of a former datum on said page via the first port, and including a writing step of a new datum to the page via the second port, taking account of the former datum.

System for writing data in a memory

The invention relates to a resistive memory including resistive elements, the resistance of each resistive element being capable of alternating between a high value and a low value, the memory further including a device for switching the resistance of at least one selected resistive element between the high and low values. The device includes a first circuit capable of circulating a first current through a first reference resistive component (R), a second circuit capable of circulating a second current proportional to the first current through the selected resistive element, a third circuit capable of detecting the switching of the resistance of the selected resistive element from the comparison of the voltage across the first reference resistive component with the voltage across the selected resistive element, and a fourth circuit capable of interrupting the second current on detection of the switching.

A system including a plurality of processing units for executing tasks in parallel and a communication network. The processing units are organized into clusters of units, each cluster comprising a local memory. The system includes means for statically allocating tasks to each cluster of units, so that a task of an application is processed by the same cluster of units from one execution to another. Each cluster includes cluster management means for allocating tasks to each of its processing units and space in the local memory for executing them, so that a given task of an application may not be processed by the same processing unit from one execution to another. The cluster management means includes means for managing the tasks, means for managing the processing units, means for managing the local memory and means for managing the communications involving its processing units. The management means operate simultaneously and cooperatively.

Statically allocating set of tasks to particular cluster and dynamically allocating each task to different processing units within cluster

An integrated circuit comprises compute nodes arranged in an array; a torus topology network-on-chip interconnecting the compute nodes; and a network extension unit at each end of each row or column of the array, inserted in a network link between two compute nodes. The extension unit has a normal mode establishing the continuity of the network link between the two corresponding compute nodes, and an extension mode dividing the network link in two independent segments that are accessible from outside the integrated circuit.

Extensible network-on-chip

The present invention relates to a quick response power supply switching device. It also relates to a power supply network equipped with such a switch. The electrical power supply is connected to a set of blocks, the device comprises at least one switch () connecting the power supply (VDD) and the block (), the value of the power supply current passing through the switch being controlled according to the difference between the power supply voltage (VDD) at the level of the other blocks and voltage threshold. The invention applies notably to all integrated circuits of recent technology in which it is important to reduce the leakage currents of the transistors in the unused circuit parts. The invention thus applies particularly to most systems powered by cell or battery and more particularly to portable telephone circuits.

Quick response power supply switching device and power supply network including such a switch

A shared memory made on a chip based on semiconductors comprising: an integer number m, greater than one, of data buses; m address and control buses; m input/output interfaces, each input/output interface being connected to one of the m data buses and to one of the m address and control buses; an integer number p, greater than one, of memory banks, each memory bank comprising: a memory, comprising a data input/output and an address and control input controlled by each of the address and control buses; a block of m switches, each of the m switches being connected on the one hand to a memory data bus, said memory data bus being connected to the data input/output of the memory, and on the other hand to one of the m data buses.

Integrating plurality of processors with shared memory on the same circuit based semiconductor

The present invention relates to a method for limiting the throughput of a communication in a meshed network, comprising the following steps: allocating fixed paths to communications likely to be established on the network; identifying the communications likely to take a mesh segment; allocating respective throughput quotas to the identified communications such that the sum of these quotas is less than or equal to a nominal throughput of said segment; and measuring the throughput of each communication at the input of the network and suspending the communication when its quota is reached.

Network on chip with quality of service

A circuit having at least one processor and a microprogrammed machine for processing the data which enters or leaves the processor in order to input or output the data into/from the circuit in compliance with a communication protocol.

Circuit comprising a microprogrammed machine for processing the inputs or the outputs of a processor so as to enable them to enter or leave the circuit according to any communication protocol

The present invention relates to a torus network comprising a matrix of infrastructure routers, each of which is connected to two other routers belonging to the same row and to two other routers belonging to the same column; and input/output routers, each of which is connected by two internal inputs to two other routers belonging either to the same row, or to the same column, and comprising an external input for supplying the network with data. Each input/output router is devoid of queues for its internal inputs and comprises queues assigned to its external input managed by an arbiter which is configured to also manage the queues of an infrastructure router connected to the input/output router.

Growing community of inventors

Saint Egreve, France

Michel Harrand