International Business Machines Corporation

Michel G Bauge

Pierre B Mollier

Gerard Boudon

Jean-Luc Peter

Yiannis J Yamour

Duplicated circuit arrangement comprising a main processor (30) and its P bit data bus (44), and two identical redundant devices (21:22), each device is comprised of a processing element (23;35) performing the same task in parallel on a P bits word, and send/receive circuits (24,25;36,37) controlled by the main processor through lines (SR11 to SR22) to transmit said word to and from said main processor. For each device, the send/receive circuits are split into two parts. Send/receive circuit of the first device (21) is split in two parts (24, 25); the first part (24) handles the P/2 Most Significant Bits (MSB's) and the second part (25) handles the P/2 Less Significant Bits (LSB's). In normal operation, during the transmission step, only the first part (24) is allowed to send bits on one half (33) of the data bus (44). Symmetrically send/receive circuit of the second device (22), is also split in two parts (36, 37); the first section (36) handles the P/2 Most Significant bits (MSB's) and the second part (37) handles the P/2 Less Significant Bits Z(LSB's); only the second part (37) is allowed to send bits on the other half (34) of the data bus (44). Therefore, the data bus driving effort is equally shared between the two devices, the maximum number of simultaneous switching is P/2 for each device. This reduction allows greater transmission speed on large busses.

Duplicated circuit arrangement for fast transmission and repairability

Integrated matrix array the points of which are defined by the intersection of the parallel lines of a first set with the parallel lines of a second set, said points being provided, or not provided, with semiconducting elements which have a first electrode connected to a line of the first set and a second electrode connected to a line of the second set, the array being of the type in which the first electrodes of the elements in each column or row are defined in a common semiconducting region, the second electrodes being provided only in the positions in which a semiconducting element is to be operative, said array being arranged such that:

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Lesigny, France

Michel G Bauge