International Business Machines Corporation

Michel F Ferry

Christian A Jacquart

Pierre Vachee

Gerard Richter

Gerard Orengo

Jean-Pierre Pantani

Daniel Ballatore

Yves A Bonnet

John Lock Creigh

Scott David Huss

Henri Braquet

Daniel F Reynes

Jean-Christophe Czarniak

Casimir Lasmayoux

Thomas Ashford Hughes, Jr

Jacques L Trehin

Gilles Catala

Andre Paci

Philippe Zeraffa

Yvan Fermier

A data transmitter is provided which performs digital to analog conversion, convolution with an arbitrary finite impulse response, and smoothing of the output functions without requiring a separate anti-aliasing low pass filter. To implement the data transmitter, a digital input data value is convolved with a desired impulse response. The coefficients of the desired finite impulse response filter are chosen to create a first or second derivative of an output of the data transmitter. Then, the derivative is integrated so that a resulting signal output from the data transmitter is a smooth signal which does not require further filtering.

Data transmitter and method therefor

A convolutional digital to analog converter (CDAC) according to the present invention enables to apply the convolution operation between the digital input signals and the Fourrier transform of a filtering transfer function. This convolution operation is combined with interleaved sampling performed by a clock splitter and also a multiplier generator device. In more details, the present convolutional DAC comprises a device splitting the incoming data for deserializing them and for sorting and storing the data in the respective N data buffers, a device splitting the clock signal (Fb) of the CDAC into N signals having a frequency equal to Fb/N clocking the respective data buffer, N multiplying DAC receiving data from the corresponding data buffer through a corresponding data bus, and N multiplier generators using identical periodic functions and being shifted by a delay respective to each other according to the clock splitter for generating the function to be convoluted with the digital inputs in the respective multiplying DACs. Second and third order for which N is equal to 1 and 2 of the convolutional DAC according to the present invention are described in detail in the description.

Convolutional digital to analog converter

This overload protection circuit capable of sustaining high capacitive load or any other load which may create an important inrush current, comprises a differential bridge composed of high impedance measuring resistors (R1, R1' R3, R3'), a low impedance sensing resistor (R2), and a timing and control circuit (20) including a transistor (T2), a capacitor (C1) and resistors that controls a switch (T1) and limits the inrush current of the subcircuit capacitor by slowing the closing of the switch. In case of defaults, the switch will be opened fast enough to minimize the fault transient transfer from down-stream to up-stream of the protection circuit. In addition, a comparator (32) associated to a resistor (R31) providing an hysteresis enables to avoid the oscillations in the region of the system transition from on to off states and vice versa. This circuit can be used in a system which comprises a secondary power supply unit (9) which powers a plurality of subcircuits (22).

Overload protection circuit capable of sustaining high inrush current in

The overload protection circuit 12 comprises a resistor bridge 20 with a low impedance sensing resistor r and high impedance resistors R1 to R4 which generates voltages Va and Vb at the inputs 32 and 34 of a comparator 22. Voltage Vb depend upon the value of the load current so that the comparator provides at its output 36 a control signal for opening the switching device 24 comprising a field effect transistor when the load current exceeds a maximum value. Resistor R5 reinforces the effect of the control signal. This circuit can be used in a system which comprises a central power supply unit 8 which powers a plurality of devices such as 4. The status of the circuit 12 is reported to the system 8 though line 14 and circuit 12 comprises a control circuit 26 which is responsive to set and reset control signals on lines 14 and 18 from the unit 8 to close or open the switch 26.

Overload protection circuit

A flexible capacitor (1) includes a dielectric made of flexible material, coated on each side with conductive material for insertion between a cable shield being at the ground potential of a remote electrical machine, and a part on a local machine being at the local ground potential (3, 5, 2) for example at a connector (7) level.

Flexible capacitor

A sigma-delta converter including a switching component controlled by a first clock having determined transitions for generating a train of sigma-delta code pulses corresponding to an analog input value. The sigma-delta includes circuits for generating a second clock of a same frequency as the first clock and having a negative transition followed after a defined period of time (d2) by a positive transition. The determined transitions of the first clock controlling the switching element occur during said defined period of time. There is also included a circuit controlled by the sigma-delta code pulse train and said second clock for generating a train of sigma-delta pulses insensitive to the mismatch of the rise and fall times of the switching element thereby improving the linearity and the signal-to-noise ratio of the converter. The control of the period of time allows varying of the energy of the pulses in order to provide pulse trains which, when applied to a sigma-delta decoder, provide an analog output value representative of, but attenuated with respect to, the analog input value.

Sigma-delta converter with improved transfer function

A conversion system is disclosed for performing either an analog-to-digital A/D conversion associated with an amplification step or a digital-to-analog D/A conversion associated with an attenuation step. The system includes apparatus (115) for receiving a input digital word to be processed, i.e. converted into analog and then attenuated, and apparatus (165) for receiving a input analog value to be processed, i.e. amplified for scaling purposes and then converted into digital. It also includes a digital-to-analog D/A converter (110), an attenuator (120) for attenuating the analog output of D/A converter (110), and a comparator (150) for comparing the value of the input analog value to be processed and the output of said attenuator (120). The processing of the D/A-attenuation process is performed by both the D/A converter (110) and attenuator (120). In order to achieve the A/D-amplification process, the system further includes generator apparatus (140) for generating a sequence of digital words to the D/A converter (110), and storage apparatus (220) for storing among this sequence, the digital value that minimizes the difference between both input of comparator (150). This digital value is extracted as being the digital representation of the amplified analog input value. Since both A/D-amplification and D/A-attenuation processings involve the same physical components, both processing have transfer function exactly inverse of one another. The typical use of this circuit is in echo cancellation technique.

Analog-to-digital and digital-to-analog conversion system and echo

A digital to analog converter for converting an N-bit digital word into its analog representation including means for splitting the N bits into n sections of N/n bits each. For instance a 12-bit word is split into an odd section and an even section which are processed independently and in parallel. This results in two partial results, V.sub.i and V.sub.p, respectively, representative of the odd and even bit sections. The last step of the conversion is the action of the two partial results V.sub.i and V.sub.p to provide the analog representation of the 12-bit word. Few operators are required to process each section because each bit is converted sequentially. This provides a low cost, compact and simple converter, moreover, since few operators are required, it may be advantageous to use high precision operators as disclosed.

Parallel algorithmic digital to analog converter

A circuit for supplying direct current to a line (a, b) from a battery via two supply resistors (RA, RB). Part of the current supplied by the battery flows in a secondary path including a resistor (R4) and a transistor (16), and is maintained at a constant value. A symmetrical and differential resistance bridge connected between the supply resistors and the line detects the transverse alternating current flowing into the battery, and means (15) are provided to cause the transistor to generate a negative-feedback alternating current whose value is adjusted to cancel said transverse alternating current.

DC Power supply circuit for line interface circuits

This interface circuit between a bidirectional line (Lg) and a telephone exchange includes a high frequency transformer (Tr) whose secondary (N2) is connected to said line through a detector circuit (DET) and whose primary (N1) is connected to the switching network of said telephone exchange and to a high frequency carrier source. The circuit further includes means for adjusting the impedances seen across the points where the telephone line is connected to the exchange, so as to meet specified values applicable to the particular location of the exchange. The impedance adaptation means include means (A1) for amplifying the line current variations seen at the center tap (K) of the high frequency transformer (Tr), addition means (.SIGMA.1) for adding the output from (A1) to the voice signal to be sent to the telephone line (Lg), and second amplification means (A2) responsive to the output from (.SIGMA.1) to drive said center tap (K).

Interface circuit with impedance adaptation means

An inductive load driving amplifier is disclosed which includes two serially connected transistors, with Zener diodes limiting the collector-emitter voltage of the one and diverting the collector-base current of the other when the first one switches off. The driver is implemented as an integrated circuit. This collector isolation constitutes a high voltage Zener diode which contributes to limit the collector voltages. The combination of these features prevents the device from being exposed to second breakdown when switching highly inductive loads (e.g. several Henrys under 50V), thereby avoiding the harmful effects of breakdowns during switching.

Inductive load driving amplifier

An active transformer is disclosed of the type which includes two primary terminals to which is applied a voltage v.sub.1 with a current i.sub.1, and two secondary terminals supplying a voltage v.sub.2 with a current i.sub.2. The transformer is characterized in that it includes a first circuit whose input, connected to the primary terminals, generates an input current of the form i.sub.1 ' = jC.sub.1 .omega.v.sub.1 and whose output supplies a current of the form i.sub.2 ' = -jN.omega.v.sub.1 to the secondary. The transformer also includes a second circuit whose input, connected to the secondary terminals, generates an input current of the form i.sub.2 ' = jC.sub.2 .omega.v.sub.2, and whose output supplies a current i.sub.1 ' = -jN.omega.v.sub.2 to the primary. The terms C.sub.1, C.sub.2 and N are respectively the dual equivalents of the terms L.sub.1, L.sub.2 and M found in the relations associated with a conventional transformer. The currents flow in such a way that they satisfy the relations i.sub.1 = i.sub.1 ' - i.sub.1 ' and i.sub.2 = i.sub.2 ' - i.sub.2 '.

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Vallauris, France

Michel F Ferry