International Business Machines Corporation

Michel Demange

Gerald Lebizay

Jean-Marie L Munier

Michel H Peyronnenc

Andrzej T Milewski

Michel A Lechaczynski

Alain Dauby

Alain Audre Couder

Alain Vedrenne

Jean-Claude Borie

Modeste Ambroise

A 3-stage switching system is provided for generating, i.e. finding, reserving and setting, path from one switch entrance port (1) to at least one switch exit port (transmit side) for asynchronously received and buffered data cells. While an Nth cell is being transferred, control means (36) generate a control word including the switch exit port address for cell (N+1)th to be subsequently transferred. Said control word is used to find and reserve a path through the switch on a stage-by-stage basis, and then set said path, if any, using a fed back acknowledgement. The (N+1)th cell path generation is performed during cell N transfer, on a cycle stealing basis.

High speed digital packet switching system

The contents of input time-division channels on a closed-loop link (10LO, 10HI) are stored in a memory (173) at the address supplied by an input address counter (IAC) controlled by an incoming timing signal (2MCR). The memory is read out under control of an output address counter (OAC) controlled by an outgoing timing signal (2MCT). Each time interval is divided into one read period and two write periods. Means (186) are provided to select one of the two write periods dependent on the phase relationship between the incoming and outgoing timing signals. The units connected in series by means of the closed-loop link receive a timing signal circulating on a timing loop (15) that is closed by a master timing device (13). Slave timing devices (18) inserted in the timing loop regenerate the timing signals circulating thereon and check same.

Synchronization system for a closed-loop multiplex communication network

A modular digital signal processor based on a master-slave architecture has the capability of expanding its processing power by aggregating additional modules in a tree type structure. In such a processor the control functions are subdivided into groups, each for performance in a distinct control unit. One or more of the control units can perform a master function with respect to one or several slaved control units and can itself be a slave to a higher level control unit. The arithmetic data functions of the processor are performed in pipe line multiplier-accumulator units (PMAU), each of which is controlled by, instructions from an associated control unit.

Modular signal processor having a hierarchical structure

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Saint Jeannet, France

Michel Demange