Motorola Corporation

Innovative Silicon S.a.

Micron Technology Incorporated

Innovative Silicon Isi Sa

Michel Bron

Richard Ferrant

Serguei Okhonin

Eric Carman

David Edward Fisch

Bruce L Morton

Anil Gercekci

Alexis Marquot

Graham Stout

Jaime Andres Borras

Raul A Pombo

Eric Boulian

Peter D Hudson

An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line via an associated isolation circuit. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, to responsively couple the associated bit line segment to or disconnect the associated bit line segment from the associated bit line.

Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same

There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

Semiconductor memory device and method of operating same

An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is coupled to an associated bit line. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, responsively connect the associated bit line segment to or disconnect the associated bit line segment from the associated bit line.

There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell includes two transistors which store complementary data states. That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary '0') and the other transistor of the memory cell stores a logic high (a binary '1'). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell. That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.

Semiconductor memory cell, array, architecture and device, and method of operating same

A method for writing data to non-volatile memory (50) involves alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). After writing, a verify erase (VE) operation and a verify program (VP) operation are performed to determine if multiple cycles are necessary. The method also permits refreshing data in the array without transferring the data onto a data bus for improved security. In one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete. The memory cell structure allows isolation of each bit in the array to avoid adverse effects on neighbor bits.

Method and apparatus for writing an erasable non-volatile memory

A method for writing to a bit of a non-volatile memory (50) by alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). Upon completion of the write operation a verify erase (VE) indication and a verify program (VP) indication are provided to a memory controller (58), which then determines if multiple cycles are necessary. The configuration of the memory cell allows isolation of each bit in the memory array to avoid effects of writes to neighbor bits. According to one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete.

Electronic devices using microprocessors requiring additional external memory can have security protection for the microprocessors while in an expanded mode of operation. A microprocessor having a security access circuit allows executable code to be stored in a peripheral storage device, such as external EPROM, while maintaining protection to the microprocessor EEPROM by monitoring if an instruction code is generated from an internal memory source or an external memory source.

Protection circuit for a microprocessor

A debit card of the type having an integrated circuit on a semiconductor chip embedded in a plastic card includes logic circuitry (10), a counter (2), a ROM (6) and an EEPROM (8) for storing the value of the counter between transactions. By providing two EEPROMs (8A, 8B) in parallel whose values are compared by a comparator (24), the security of the card is increased since operation of the card may be blocked if the two values are not the same, indicating that attempts have been made to fraudulently reprogram the card.

Memory cards

An integrated circuit for a data or 'smart' card includes a non-volatile memory (8) having a transport code preprogrammed therein, control circuitry (10), a comparator (24) for comprising an externally-applied code and the transport code, and a fuse (26) which is blown if the two codes match thereby allowing the card to be initialised with a personal identification number and initial credit values. A second fuse (28) may also be provided which is blown if the two codes do not match and sensing means (32, 34) sense the status of the two fuses (26, 28) and block any further attempts to initialise the card if the second fuse (28) is blown and the first fuse (26) is not.

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Lausanne, Switzerland

Michel Bron