Iroc Technologies

Lroc Technologies

Michaël Nicolaidis

Slimane Boutobza

An integrated circuit chip comprising a number of semiconductor components exhibiting parasitic components through which a short-circuit between the circuit supply voltage and ground could occur, wherein said semiconductor components are distributed in elementary blocks, each elementary block being independently connected, for its power supply, to the supply or ground lines of the main supply network of the integrated circuit by a current-limiting device capable of stopping a short-circuit starting in the considered block, and each block being sized so that logic errors occurring in this block are correctable by error-correction means.

Integrated circuit protected against short circuits and operating errors following the passage on an ionizing radiation

The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (), having at least an output (A); a circuit () generating an error control code for said output, and a storage element () provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.

Logic circuit protected against transient disturbances

A programmable built in self test, BIST, system for testing a memory, comprises an instruction register formed in the same chip as the memory; a circuit for loading the register by successive instructions, each instruction comprising at least one address control field, a first number (m) of operation fields, a number-of-operations field specifying a second number t+1, with t+1&#x2266;m; a circuit controlled by the address control field to determine successive addresses; and a cycle controller for executing, for each successive address, the second number (t+1) of successive operations, each of which is determined by one of the t+1 first operation fields.

Programmable test for memories

A device for reconfiguring faults in a circuit comprised of several units and comprising storage means for storing the fault locations, connection/disconnection means for disconnecting faulty units and connecting in their place fault-free units, and means for generating control signals of the connection/disconnection means, responding to the content of the storage means. According to this method, each unit is divided into several portions; in a test phase, fault tests are carried out for the different units, and the test results of the different portions of the units are stored in the storage means; and in a use phase aiming at the use of given unit portions, said control signals are determined by the content of the storage means corresponding to these unit portions.

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Saint Egreve, France

Michaël Nicolaidis