Synopsys, Inc.

Michal J Rewienski

Kevin J Kerns

A method for optimizing post-layout array for accelerated transistor level simulation is provided. In some embodiments of the present invention, a post-layout array of cells having a plurality array lines is optimized by forming array line models for the array lines of the post-layout array of cells. Ideal sub-arrays are formed with the cells of the post-layout array. The ideal sub-array can be simulated using conventional techniques such as HAR or SOFA. Furthermore, some embodiments of the present invention also detect and optimize parasitic capacitors to facilitate formation of the ideal sub-arrays.

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San Francisco, CA, United States of America

Michal J Rewienski