Spin Memory, Inc.

Integrated Silicon Solution, (cayman) Inc.

Spin Transfer Technologies, Inc.

Integrated Silicon Solution Incorporated

Michail Tzoufras

Marcin Gajek

Kadriye Deniz Bozdag

Eric Ryan

Mourad El Baraji

Kuk-Hwan Kim

Dafna Beery

Satoru Araki

Mustafa Pinarbasi

Andrew J Walker

Bartlomiej Adam Kardasz

Davide Guarisco

Andy Walker

Amitay Levi

Elizabeth Ann Dobisz

Gian Sharma

Girish Jagtiani

Mustafa Michael Pinarbasi

A computing device includes one or more processors, a first random access memory (RAM) comprising magnetic random access memory (MRAM), a second random access memory of a type distinct from MRAM, and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The computing device receives first data on which to train an artificial neural network (ANN) and trains the ANN by, using the first RAM comprising the MRAM, performing a first set of training iterations to train the ANN using the first data, and, after performing the first set of training iterations, using the second RAM of the type distinct from MRAM, performing a second set of training iterations to train the ANN using the first data. The computing device stores values for the trained ANN. The trained ANN is configured to classify second data based on the stored values.

System and method for training artificial neural networks

A computing device includes one or more processors, random access memory (RAM), and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The computing device receives first data and classifies the first data using a neural network that includes at least one quantized layer. The classifying includes reading values from the random access memory for a set of weights of the at least one quantized layer of the neural network using first read parameters corresponding to a first error rate.

System and method for classifying data using neural networks with errors

Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.

Patterned silicide structures and methods of manufacture

A computing device receives first data on which to train an artificial neural network (ANN). Using magnetic random access memory (MRAM), the computing device trains the ANN by performing a first set of training iterations on the first data. Each of the first set of iterations includes writing values for a set of weights of the ANN to the MRAM using first write parameters corresponding to a first write error rate. After performing the first set of iterations, the computing device performs a second set of training iterations on the first data. Each of the second set of iterations includes writing values for the set of weights of the ANN to the MRAM using second write parameters corresponding to a second write error rate. The second write error rate is lower than the first write error rate. The computing device stores values for the trained ANN.

A computing device includes one or more processors, random access memory (RAM), and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The computing device receives first data on which to train a neural network comprising at least one quantized layer and performs a set of training iterations to train weights for the neural network. Each training iteration of the set of training iterations includes stochastically writing values to the random access memory for a set of activations of the at least one quantized layer of the neural network using first write parameters corresponding to a first write error rate. The computing device stores trained values for the weights of the neural network. The trained neural network is configured to classify second data based on the stored values.

System and method for training neural networks with errors

A magnetic memory device comprises a cylindrical core and a plurality of layers surrounding the core. The plurality of layers include a metallic buffer layer, a ferromagnetic storage layer, a barrier layer, and a ferromagnetic reference layer. The cylindrical core, the metallic buffer layer, the ferromagnetic storage layer, the barrier layer, and the ferromagnetic reference layer collectively form a magnetic tunnel junction. A magnetization of the ferromagnetic layer storage parallels an interface between the metallic buffer layer and ferromagnetic storage layer.

Three-dimensional (3D) magnetic memory devices comprising a magnetic tunnel junction (MTJ) having a metallic buffer layer

A method is performed at an electronic device that includes magnetic random access memory (MRAM). The method includes loading the MRAM with data including main data, first error correcting data, and second error correcting data. The MRAM comprises a plurality of MRAM cells characterized by a first magnetic anisotropy corresponding to a first error rate at a predefined temperature that exceeds a threshold for correcting errors using only the first error correcting data. The method further includes, after loading the MRAM with the data, heating the MRAM to the predefined temperature and correcting errors in the main data using both the first error correcting data and the second error correcting data. The method further includes after correcting the errors in the main data, erasing, from the MRAM, the second error correcting data and maintaining, on the MRAM, the first error correcting data.

Error recovery in magnetic random access memory after reflow soldering

A method for crystalized silicon structures from amorphous structures in a magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSior CoSiand also causes the underlying amorphous silicon to crystallize.

High density MRAM integration

The various implementations described herein include magnetic memory devices and systems, and methods for propagating defects in the devices and systems. In one aspect, a magnetic memory device comprises a non-magnetic cylindrical core configured to receive a current, a plurality of magnetic layers surrounding the core, and a plurality of non-magnetic layers also surrounding the core. The magnetic layers and the non-magnetic layers are arranged in a stack coaxial with the core. Respective magnetic layers of the plurality of magnetic layers are separated by respective non-magnetic layers of the plurality of non-magnetic layers. The device further comprises an input terminal coupled to a first end of the core and a current source coupled to the input terminal. The current source is configured to supply current imparting a Spin Hall Effect (SHE) around the circumference of the core, and the SHE contributes to a magnetization of the magnetic layers.

Defect propagation structure and mechanism for magnetic memory

A method for selectively writing to STT-MRAM using an AC current is provided. The method is performed in a memory device including two or more multilevel magnetic tunnel junctions (MTJs) arranged in series with respect to a single terminal of a transistor, where the two or more multilevel MTJs include a first MTJ having a first magnetic characteristic and first electrical characteristic and a second MTJ having a second magnetic characteristic that is distinct from the first magnetic characteristic and a second electrical characteristic. The method includes writing to an MTJ. The writing includes applying a DC current to the two or more MTJs and applying an AC current to the two or more MTJs, where the AC current is adjusted to a frequency that is tuned to a write assist frequency corresponding to the respective MTJ.

Methods and systems for writing to magnetic memory devices utilizing alternating current

The various implementations described herein include methods, devices, and systems for fabricating magnetic memory devices. In one aspect, a method of fabricating a magnetic memory device includes: (1) providing a dielectric substrate with a metallic core protruding from the dielectric substrate, where: (a) a first portion of the metallic core is surrounded by the dielectric substrate and a second portion of the metallic core protrudes away from a surface of the dielectric substrate; and (b) the second portion includes: (i) a surface offset from the surface of the dielectric substrate and (ii) sidewalls extending away from the surface of the dielectric substrate to the offset surface; (2) depositing a first ferromagnetic layer on exposed surfaces of the metallic core and the dielectric substrate; (3) depositing a spacer layer on exposed surfaces of the first ferromagnetic layer; and (4) depositing a second ferromagnetic layer on exposed surfaces of the spacer layer.

Methods of fabricating three-dimensional magnetic memory devices

The various implementations described herein include magnetic memory devices and systems, and methods for injecting defects into the devices and systems. In one aspect, a magnetic memory device comprises a non-magnetic cylindrical core, a first portion, and a second portion. The core is configured to receive a current. The first portion surrounds the core and is configured to introduce magnetic instabilities into the second portion. The second portion is adjacent to and arranged in a stack with respect to the first portion. The second portion also surrounds the core and is configured to store information based on a respective position of the magnetic instabilities. The second portion comprises a first plurality of magnetic layers and a first plurality of non-magnetic layers. Respective magnetic layers of the first plurality of magnetic layers are separated by respective non-magnetic layers of the plurality of non-magnetic layers.

Defect injection structure and mechanism for magnetic memory

Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to switch the state of a corresponding one of N cell elements of the MBC. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.

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Sunnyvale, CA, United States of America

Michail Tzoufras