Intel Corporation

International Business Machines Corporation

Michael Zelikson

Norbert Unger

Efraim Rotem

David Goren

Shai Rotem

Kosta Luria

Eyal Fayneh

Alexander Lyakhov

Rachel Gordin

Vjekoslav Svilan

Gregory Sizikov

Lior Gil

Alon Naveh

Joseph Shor

Israel A Wagner

Amit Kumar Jain

Sameer Shekhar

Nimrod Angel

Gennady Burdo

Betty Livshitz

Amir Alon

Yuri Bruck

Eliezer Weissmann

Varghese George

Sanjeev S Jahagirdar

Doron Rajwan

Naveen Neelakantam

Stephen H Gunther

Fabrice Paillet

Nadav Shulman

Inder M Sodhi

Eugene Gorbatov

Nir Rosenzweig

Harish Krishnamurthy

Alexander Uan-Zo-Li

Chee Lim Nge

Anant S Deval

Chin Lee Kuan

Alex Waizman

Philip R Lehwalder

Arik Gihon

Khondker Z Ahmed

Donald J Papae

Moshe Leibowitz

Sergio Carlo Rodriguez

Patrick K Leung

Kelvin Kwan

Yevgeny Perelman

Eliyahu Shamsaev

Vishram Shriram Pandit

Alexander Waizman

Sherman Anatoly

Anatoly Sherman

Liby Boreysha

Vadim Goldenberg

A supply voltage may be set using a local voltage regulator, such as a Digital Linear Voltage Regulators (DLVR). A DLVR may include a compensator, and the performance of the compensator may be affected by a dropout (DO) voltage. To improve the performance of a compensator, a number of compensator calculations may be pre-calculated to reduce the complexity of remaining real-time computations and enable compensator calculations to be completed within a single DLVR clock cycle. A DLVR may include a sense filter, and the DLVR transfer function (TF) may be modified using dynamic shaping of open loop gain and pole locations of a sense filter. The DO range associated with the DLVR TF may be changed according to a monitored DO(t) to reduce the sensitivity of a domain VMIN on dropout, which reduces power consumption, increases performance, and enables simplification of test flows.

DLVR-supplied logic domain operational voltage optimization

Some embodiments include an apparatus including a first node in a voltage regulator, a second node in the voltage regulator, and a power stage to receive a first voltage from the first node and provide a second voltage at the second node. The power stage includes a first circuit path and a second circuit path coupled in parallel with each other between the first and second nodes. The first circuit path includes a first number of at least one transistor coupled between the first and second nodes. The second circuit path includes a second number of at least one transistor between the first and second nodes. Wherein the first number is unequal to the second number.

Digital voltage regulator including mixed-stack power stage

The circuits and methods described herein provide technical solutions for technical problems facing power driver circuits. To reduce or eliminate effects associated with a gate capacitance discharge current and inconsistent effective V, the discharge process may be split into two phases. During a first phase, the transistor gate charge is drained into ground through a large path gate. The ground (GND) features a very low impedance, hence the resulting δV(t)|is negligible even for high discharge currents. The transistor gate node voltage (V) is constantly monitored, and the discharge process switches from the first phase to the second phase when Vtransgresses a bias voltage threshold based on the target value of V. To switch from the first phase to the second phase, the current path into GND is cut by switching its path gate to an OFF state, and an alternative path is enabled between transistor gate charge and V.

Efficient switching of output stage power driver

Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.

Apparatus and method for proactive power management to avoid unintentional processor shutdown

A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Digital linear regulator clamping method and apparatus

An apparatus is provided which comprises: a first voltage regulator; a second voltage regulator; and a switch to selectively couple the first voltage regulator to the second voltage regulator, such that a first output node of the first voltage regulator is temporarily coupled to a second output node of the second voltage regulator via the switch.

Apparatus, system, and method for reducing voltage overshoot in voltage regulators

Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.

Methods and systems to control power gates during an active state of a gated domain based on load conditions of the gated domain

Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.

Low dropout voltage regulator integrated with digital power gate driver

A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power-gate circuit even in cases where the duration of the idle mode may be short.

Charge-saving power-gate apparatus and method

Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.

Efficient integrated switching voltage regulator comprising switches coupled to bridge drivers to provide regulated power supply to power domains

A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power gate circuit even in cases where the duration of the idle mode may be short.

In one embodiment, the present invention includes an apparatus having an estimation logic to estimate a dynamic capacitance of a processor circuit of a processor during a plurality of processor cycles, a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the processor circuit based on the dynamic capacitance estimate, and a controller to control an impedance of the power gate circuit based on the control value. Other embodiments are described and claimed.

Controlling power gate circuitry based on dynamic capacitance of a circuit

Efficient integrated switching voltage regulator

Growing community of inventors

Haifa, Israel

Michael Zelikson