Motorola Corporation

Michael Zarubinsky

Vladimir Koifman

Yachin Afek

Eliav Zipper

Ronen Paz

Yoram Salant

Natan Baron

Leonid Tsukerman

Eliezer Sand

David Moshe

Konstantin Berman

In a radio circuit (299) that forwards a signal pair (I,Q) by first ( , I) and second ( , Q) channels, by converting the signal pair (I,Q) from a digital form (I , Q ) to an analog form (I , Q ), a gain controller ( ) monitors differences between the overall gains (G , G ) in the channels and corrects a gain imbalance by feeding back a gain determining control signal (W) to one of the channels. The gain controller ( ) has digital comparators ( ) at the inputs ( ) of the channels and analog comparators at the outputs ( ) of the channels. Intrinsic offsets of the analog comparators are determined and compensated by subtracting corresponding offsets from the digital comparators.

Gain controller with comparator offset compensation for circuit having in-phase and quadrature channels

In a radio circuit ( ) that forwards a signal pair (I,Q) by a first channel ( , I) and by a second channel ( , Q), a gain controller ( ) monitors differences between the overall gains (G , G ) in the channels and corrects a gain imbalance by feeding back a gain determining control signal (W) to one of the channels. The controller has first ( ) and second ( ) pluralities of single-bit comparators, operating at a high sampling rate, to monitor the signal pair at the channel inputs ( ) and at the channel outputs ( ), respectively, and to provide difference signals (&Dgr;X,&Dgr;Y) to an integrator ( ) that calculates the gain control signal (W) at a decimated sampling rate (F ).

Gain controller for circuit having in-phase and quadrature channels, and method

A phase lock loop having an bandwidth that does not depend upon N. The phase lock loop comprising: a controlled oscillator, a frequency divider by N, a phase detector for producing an error signal ER, and an adjustable converter, coupled to the phase detector and to the current controlled oscillator, for receiving ER and providing the controlled oscillator a control signal such that that the (Fico/N) ranges between a minimum value of Fmin and a maximal value of Fmax, wherein Fref&equals;(Fmin&plus;Fmax)/2.

Phase lock loop having a robust bandwidth and a calibration method thereof

A signal generator ( ) receives an input clock signal (X ) at a first frequency (F ) and derives an output clock signal (Y) at a second frequency (F ). An arrangement ( ) using a first intermediate signal (Z) receives the input clock signal (X ) and provides a second intermediate signal (X ) by selectively providing transitions ( ) of the second intermediate signal (X ) at time intervals (T (n)) that are determined by a variable number (A&plus;P(n)) of periods (T ) of the first intermediate signal (Z). The second intermediate signal (X ) has a frequency (F ) that is in average (F&prime; ) higher than the first frequency (F ). A phase-looked loop (PLL) circuit ( ) locks at this average frequency (F&prime; ) and provides the output clock signal (Y).

Signal generator, and method

An analog-to-digital converter (,) has a first stage (,) to integrate and quantize the difference between a feedback signal (R) and an input signal (X) to a first intermediate signal (Y,) with a first resolution (M,), a second stage (,) to integrate and quantize the first intermediate signal (Y,) to a second intermediate signal (Y,) with a second, lower resolution (M,), a feedback stage (,) to convert the second intermediate signal (Y,) to the feedback signal (R), and a third stage (,) to differentiate the first intermediate signal (Y,) to a third intermediate signal (W,), to delay the second intermediate signal (Y,) to a fourth intermediate signal (W,), and to add the third and fourth intermediate signals (W,, W,) to an output signal (Y) having a resolution that results from the sum of the first (M,) and second (M,) resolutions.

Delta-sigma analog-to-digital converter, and method

The Viterbi algorithm (,) is performed with a reduced number of calculations when the comparing step (C,,) is anticipated before the selecting (S,,) and adding steps (A,,). During comparing (C), selection decisions (e.g., D (i)) are obtained by analyzing pairs of old path metrics (e.g., P (2i, j&minus;1) at 91, P (2i&plus;1, j&minus;1) at 92) by subtracting and multiplying the path metrics with branch metrics (e.g., B (i, j) at 95) and combining intermediate sign (e.g., SP, SB, S&Dgr;) by e.g., and-logic (,). Selecting decisions (e.g., D (i/2, j&plus;1), D (i/2&plus;N/2, j&plus;1) and new path metrics (e.g., P (i, j), P (i&plus;12, j) are continuously stored and updated.

Apparatus and method for implementing viterbi butterflies

A phase locked loop PLL has a current controlled oscillator ICO, having an input resistance Rin. Rin is proportional to a control current Idac sent to ICO. ICO is coupled to a capacitor, the capacitor and Rin introduce a pole Fpole in the transfer function of PLL. The PLL further has a sigma delta modulator, for providing a digital sigma delta modulated control signal SDO, SDO is converted to an analog control current Idac, that is provided to ICO and smoothed by Rin and the capacitor. The sigma delta modulator forces error signal outside a predetermined frequency BWsd; and Fpole tracks BWsd.

Low jitter phase locked loop having a sigma delta modulator and a method thereof

A device and a method for canceling DC offset resulting from digital to analog conversion, wherein the device is coupled to a digital to analog comparator (i.e.&mdash;DAC), the device comprising of: an adder, coupled to the DAC, for adding a digital input signal IN(n) to a compensation signal CS(w&minus;1), and sending the sum of IN(n) CS(w&minus;1) to the DAC. An analog comparator, coupled to the DAC, for sampling the output signal OUT(t) of the DAC, for comparing the sampled signal ACS(n) to a first reference voltage VREF and for outputting a signal ACO(n) which represents the result of the comparison between ACS(n) and VREF. A DAC emulator, coupled to the DAC, for compensating for a time lapse between the appearance of a digital input signal IN(n) appearing at the input of the adder and an OUT(t), wherein OUT(t) resulted from IN(n). A digital comparator for receiving the output signals DES(n) of the DAC emulator, comparing DES(n) to a second reference value DREF and outputting a signal DCO(n) which represents the result of the comparison between DES(n) to DREF, and an offset calculation unit, coupled to the analog comparator and to the digital comparator for comparing ACO(n) and DCO(n) and sending to the adder, a compensation signal CS(n) which represents the result of the comparison between ACO(n) and DCO(n). The analog and digital comparator are driven by a clock signal which is not correlated to IN(n).

Digital to analog convertor having a DC offset cancelling device and a method thereof

A phase detector and a method for detecting phase difference between two high frequency signals, the phase detector is adapted to receive a reference signal REF, a high frequency signal ICOS, and a signal FD synchronized to ICOS. REF, ICOS and FD have opposite edges. The phase detector comprising of: An asynchronous phase detector circuit, for providing an asynchronous control signal CTP, for representing a time interval between a time of occurrence of an edge of REF and the time of occurrence of a corresponding edge of ICOS. A synchronous phase detector circuit, for providing an synchronous control signal TC, for representing a time interval between a time of the occurrence of the corresponding edge of ICOS and the time of occurrence of a corresponding edge of FD.A combing circuit, for receiving TC and CTP and providing an error signal ERS, representing the phase difference between REF and FD.

High speed phase detector and a method for detecting phase difference

A digital-to-analog converter (200) has a first portion (208) which receives a digital input signal X (201') and has serially coupled a second portion (209) which provides an analog output signal Y (202'). The first portion (208) is a delta-sigma modulator with integrators (210 and 215), adders (203 and 205), a comparator (220) and delay stages (230 and 235). The second portion (209) comprises a commutator (260), unit converters (280-n) and an analog adder (290). In the second portion, the unit converters (280-n) can be mismatched. The first portion (208) provides a noise-shaped intermediate signal V (221') which has substantially zero noise at that frequencies where the mismatches would lead to unwanted spectral tones.

Digital-to-analog converter with noiseshaping modulator, commutator and

A rational decimation circuit (200) has an integration filter (210) and an FIR-filter (220). The integration filter (210) has N serially arranged integrator blocks (230-n) and an interpolator block (250). The FIR-filter (220) has K filter channels (260-k) and a commutator (290) which are controlled by a control block (300). Each channel (260-k) has a multiplier unit (270-k) and an accumulator unit (280-k). The integration filter (210) has a transfer function with N-fold poles and the FIR-filter (220) has a transfer function with zeros which cancel the poles. FIR-coefficients h.sub.k (T.sub.V) in the FIR-filter (220) are related to the F.sub.V /F.sub.X ratio of the interpolator block (250) and to the number N of integrator blocks (230-n). A method is also described.

Apparatus and method for sampling rate conversion with rational factors

An analog-to-digital converter (100) has a first path (110) with a first sigma-delta modulator (114) which transforms an analog input signal X.sub.0 (111') from an input terminal (101) to a digital output signal Y.sub.0 at an output terminal (102). In a second path (120), a digital dither signal D (121') is combined with a digital intermediate signal Z.sub.0 (115') from the first modulator (114) and digitally processed by a second sigma-delta modulator (124) to an intermediate signal Y.sub.1 (125') Y.sub.1 is fed to the first modulator (114) and to the output terminal (102) with opposite sign ('+' and '-', respectively). Thereby, multipliers (133 and 127) attenuate Y.sub.1. The dither signal D (121') is used substantially only within the converter (100), and is substantially canceled before the output terminal (102). This features preserve a high SNR of the converter (100) and low spectral tones in output signal Y.sub.0.

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Jerusalem, Israel

Michael Zarubinsky