Xilinx, Inc.

Michael Zapke

Ramesh R Subramanian

Ravinder Sharma

Jayaram Pvss

Manjunath Chepuri

A circuit for memory access includes a memory access control circuit. The memory access controller is coupled to a memory and configured to perform data transfers to retrieve data from the memory. The memory access control circuit includes a timing control circuit and a transfer control circuit. The timing control circuit is configured to determine first timing information based on a timing requirement for transmitting a first data stream to a first network; and determine a first fetch time for retrieving the first data stream from the memory based on the first timing information. The transfer control circuit is configured to retrieve the first data stream from the memory based on the first fetch time.

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Munich, Germany

Michael Zapke