Mentor Graphics Corporation

Nxp B.v.

Michael Wittke

Friedrich Hapke

Reinhard Meier

Juergen Schloeffel

Thomas Hans Rinderknecht

Rene Krenz-Baath

Sascha Ochsenknecht

On-chip high speed clock control techniques for testing circuits with multiple clock systems are disclosed. The techniques allow certain (e.g. compatible) high speed clocks to be activated with predefined waveforms during a capture period of a logic test, based on a clock control signal. The clock control signal may be supplied via a JTAG control port or via a scan chain load port. The clock control signal may also be generated by a BIST controller. The techniques may ensure glitch-free transitions from slow speed clocks during a shift period to fast speed clocks during a capture period.

High speed clock control

On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further include comparator circuitry to produce an output signal by comparing the test signature with the fault-free signature or by first compressing the test signature and then comparing the compressed test signature with the compressed fault-free signature.

On-chip logic to log failures during production testing and enable debugging for failure diagnosis

An integrated circuit (IC) is disclosed that comprises a circuit portion () having a plurality of inputs () and a plurality of outputs (), the plurality of inputs being arranged to receive a test pattern in a test mode of the integrated circuit, the test pattern comprising a plurality of test vectors for feeding to the plurality of inputs in successive clock cycles. The IC also comprises a test arrangement for testing the circuit portion (), comprising a test pattern generator () for generating the test pattern, masking logic () for masking selected outputs of the plurality of outputs () and a signal generator () coupled to the masking logic () for generating a masking signal triggering the masking of all of said circuit portion outputs during selected cycles of the successive clock cycles, the signal generator () being responsive to clock cycle selection data (s-s). This way, selected clock cycles or individual flip-flops can be masked out without requiring external control signals. The IC may also comprise a mask storage arrangement () for storing masks to mask a plurality of scan chains for all cycles within a pattern.

Testable integrated circuit and test data generation method

Techniques for storing and using compressed restrict values for selected scan chains and flip-flops, such that the states that need to be applied to those flip flops need not be solved by a linear equation system solver, such as a linear equation system solver provided by an automatic test pattern generation (ATPG) tool. Selected restrict values can then be injected into test patterns for those flip-flop combinations that need to be set in a certain shift cycle or those flip-flops that need to be initialized one after another (e.g., for serial settings in one scan chain).

Deterministic logic built-in self-test stimuli generation

Techniques are provided for X-masking using at least some masking information provided by on-chip logic, in lieu of masking information provided from off of the integrated circuit being tested. The masking information is provided by a masking information source on the integrated circuit being tested, such as, for example, a read-only memory (ROM) circuit, that feeds the masking information to the X-masking logic. With these implementations of the invention, it is possible to perform X-masking independent from any external data, thus enabling X-masking for a logic built-in self-test without requiring an external testing device.

On-chip logic to support compressed X-masking for BIST

According to an example embodiment, there is an integrated circuit arrangement with at least one application circuit to be tested, and with at least one self-test circuit for testing the application circuit and generating at least one pseudo-random test sample. wherein said The pseudo-random test sample is converted into at least one test vector that is programmable and/or deterministic and is supplied to the application circuit for testing purposes via at least one logic gate and at least one signal that is applied to said logic gate. The output signal arising in dependence on the deterministic test vector is evaluated by the application circuit by at least one signature register. Furthermore, there is a method of testing the application circuit such that Built In Self Test (BIST) hardware connected to the additional deterministic logic is reduced; it is suggested that the signal supplied to the logic gate is made available by a Bit Flipping Function (BFF) logic circuit based on at least one self-test circuit.

Growing community of inventors

Pinneberg, Germany

Michael Wittke