International Business Machines Corporation

Other

Samsung Electronics Co., Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Michael Wayne Lane

Thomas M Shaw

Daniel C Edelstein

Vincent James McGahay

Anthony K Stamper

Timothy Joseph Dalton

Xiao Hu Liu

Jeffrey P Gambino

Stephen McConnell Gates

Andrew Herbert Simon

Edward Crandal Cooney, Iii

Son Van Nguyen

Elbert Emin Huang

John Anthony Fitzsimmons

Satyanarayana Venkata Nitta

Stefanie Ruth Chiras

Sampath Purushothaman

Matthew Earl Colburn

Alfred Grill

Robert Rosenberg

Eric Gerhard Liniger

Lee Matthew Nicholson

Sujatha Sankaran

Lawrence Alfred Clevenger

Conal Eugene Murray

Deborah A Neumayer

Darryl D Restaino

Chih-Chao Yang

Robert Dennis Miller

Griselda Bonilla

Yun-Yu Wang

William Thomas Motsiff

Fenton Read McFeely

James J Demarest

Philip L Flaitz

Chester T Dziobkowski

James R Lloyd

Shom Ponoth

Mukta G Farooq

Qinghuang Lin

Sanjay C Mehta

Sandra Guy Malhotra

Terry Allen Spooner

Christos Dimitrios Dimitrakopoulos

Howard Smith Landis

Robert Hannon

James Patrick Doyle

Derren Neylon Dunn

Deepak Anantarao Kulkarni

Philippe Mark Vereecken

Ian D W Melville

Xio Hu Liu

Theodorus E Standaert

Hariklia Deligianni

Kenneth Parker Rodbell

Paul Stephen Andry

Edmund Juris Sprogis

Roy Rongqing Yu

Jae Hun Kim

Gareth Geoffrey Hougham

George Frederick Walker

Jon Alfred Casey

Chandrasekhar Narayan

Jeffrey Curtis Hedrick

David L Questad

Vishnubhai Vitthalbhai Patel

Carlos Juan Sambucetti

Shyng-Tsong Chen

Cornelia K Tsang

Kaushik Arun Kumar

Panayotis Constantinou Andricacos

Raymond R Horton

Hormazdyar M Dalal

Brian Richard Sundlof

Chirag Suryakant Patel

William Francis Landers

Hazara Singh Rathore

Christy Sensenich Tyberg

Kelly Malone

Matthew S Angyal

Habib Hichri

Du Binh Nguyen

Michelle Leigh Steen

Sherif Ahmed Goma

Johnny Widodo

Birendra N Agarwala

Leena Paivikki Buchwalter

Wilma Jean Horkans

Ernest N Levine

Jawahar P Nayak

Keith Thomas Kwietniak

Jeffrey R Marino

Peter E Biolsi

Bernd E Kastenmeier

Conrad A Barile

Fenton Reed Mc Feely

Darren N Dunn

Satyanayana V Nitta

Robert Rosenburg

Brett H Engle

An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.

Semiconductor chips including passivation layer trench structure

Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.

Device and methodology for reducing effective dielectric constant in semiconductor devices

Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

Reducing effective dielectric constant in semiconductor devices

A method of fabricating a low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided. The method includes the deposition of the dielectric material from a first precursor which is an carbosilane or an alkoxycarbosilane molecule.

Method of fabricating a SiCOH dielectric material with improved toughness and improved Si-C bonding

A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures

Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures

Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si&#x2014;CHfunctional groups, and another fraction of the C atoms are bonded as Si&#x2014;R&#x2014;Si, wherein R is phenyl, &#x2014;[CH]&#x2014; where n is greater than or equal to 1, HC&#x2550;CH, C&#x2550;CH, C&#x2261;C or a [S]linkage, where n is a defined above.

SiCOH dielectric material with improved toughness and improved Si-C bonding

A chip is provided which includes a back-end-of-line ('BEOL') interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric ('ILD') layers which include a dielectric material curable by ultraviolet (&#x201c;UV&#x201d;) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.

BEOL interconnect structures with improved resistance to stress

In integrated circuit technology; an electromigration and diffusion sensitive conductor of a metal such as copper and processing procedure therefore is provided, wherein, at a planarized chemical mechanical processed interfacing surface, the conductor metal is positioned in a region of a selectable low K eff dielectric material surrounded by a material selected to be protection from outdiffusion and a source of a film thickness cap that is to form over the conductor metal and/or serve as a catalytic layer for electroless selective deposition of a CoWP capping .

Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures

An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO&#x2014; or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Structure to improve adhesion between top CVD low-K dielectric and dielectric capping layer

Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

Dual damascene interconnect structures having different materials for line and via conductors

The present invention provides a method of strengthening a structure, to heal the imperfection of the structure, to reinforce the structure, and thus strengthening the dielectric without compromising the desirable low dielectric constant of the structure. The inventive method includes the steps of providing a semiconductor structure having at least one interconnect structure; dicing the interconnect structure; applying at least one infiltrant into the interconnect structure; and infiltrating the infiltrant to infiltrate into the interconnect structure.

Strengthening of a structure by infiltration

Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.

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Cortlandt Manor, NY, United States of America

Michael Wayne Lane