International Business Machines Corporation

Michael Wayne Harper

Mack Wayne Riley

Christopher W Steffen

Robert Christopher Dixon

Glen Arthur Wiedemeier

Arden Lot Moore

Ethan E Cruz

Michael B Spear

Erik English

Chad Andrew Marquart

Dereje G Yilma

Ryan Michael Kruse

Venkat Harish Nammi

Brian G Veraa

Jeffrey Kwabena Okyere

Vikram B Raj

Nathan Ross Blanchard

Steven R Carlough

Gary A Van Huben

Larry Scott Leitner

Susan M Eickhoff

John G Rell, Iii

Ra'ed M Al-omari

Cindy Phan

James Crugnale

Aspects of the invention include a phase rotator, that is located at a built-in self-test (BIST) path of a receiver, receiving a clock signal from an on-chip clock. The phase rotator shifts the phases of the clock signal. The phase rotator transmits the shifted clock signal to a binary sequence generator, that is located at the receiver. The binary sequence generator outputs a binary sequence, where the binary sequence generator is driven by the shifted clock signal.

Self-contained built-in self-test circuit with phase-shifting abilities for high-speed receivers

Aspects of the invention include a driver arranged at a stand-alone receiver that is configured to receive a binary sequence from a pseudorandom binary sequence (PRBS) generator arranged at the receiver. The driver is configured to adjust the signal characteristics of the binary sequence to simulate channel loss at the receiver. The driver is further configured to output the adjusted binary sequence to a downstream data path of the receiver to enable the receiver to perform a self-test.

Built-in-self-test and characterization of a high speed serial link receiver

A calibration controller of a receiving chip learns a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of the receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary. The calibration controller dynamically adjusts a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.

Reducing chip latency at a clock boundary by reference clock phase adjustment

Method and apparatus for packeted analysis, comprising: testing a phase rotator at a plurality of phase rotator positions, by propagating a first series of bits of a first pattern through a channel of an integrated circuit; propagating a second series of bits of a second pattern through the channel; measuring, for the given phase rotator position, a value of each bit propagated through the channel; and in response to determining that measured values of the bits propagated through the channel conform to one of the first pattern and the second pattern, indicating that the given phase rotator position satisfies an accuracy threshold; determining a sequence of phase rotator positions of the plurality of phase rotator positions in which the accuracy threshold is satisfied; and in response to determining that the sequence of phase rotator positions does not satisfy an eye width threshold, failing the channel of the integrated circuit.

Built-in self-test for receiver channel

An anti-counterfeiting technique presents, to a test thermoreflective mark at a first temperature, a first electromagnetic wave. A first test reflective profile for the test thermoreflective mark associated with the first temperature is recorded. A second electromagnetic wave is presented to the test thermoreflective mark at a second temperature. A second test reflective profile for the test thermoreflective mark associated with the second temperature is recorded. The first test reflective profile is compared with a first control reflective profile that is associated with a genuine thermoreflective mark. The second test reflective profile is compared with a second control reflective profile that is associated with the genuine thermoreflective mark.

Anti-counterfeiting opto-thermal watermark for electronics

Some embodiments of the inventive subject matter include a computer program product for validating a test thermoreflective mark. The computer program product can include computer usable program code configured to control a temperature regulation unit configured to govern a temperature of a thermoreflective mark. The computer usable program code can be further configured to control an electromagnetic waver emitter to present at a first temperature, a first electromagnetic wave. The computer usable program code can be further configured to record a first reflective profile. The computer usable program code can be further configured to control the electromagnetic wave emitter to present at a second temperature, a second electromagnetic wave. The computer usable program code can be further configured to record a second reflective profile. The computer usable code can be further configured to validate the thermoreflective mark based on the first reflective profile and the second reflective profile.

An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.

On-chip detection of types of operations tested by an LBIST

A mechanism is provided for identifying a failing latch within an integrated circuit device. A test sequence is initiated on a set of scan chains associated with an identified failing multiple input signature register. For each test portion in a set of test portions in the test sequence, a comparison is performed between an output of the multiple input signature register and a corresponding value in a set of expected values. Responsive to determining a match, a value of a counter is incremented. Responsive to a failure to match, incrementing of the counter is stopped, and the value of the counter providing an indication of the failing latch in the integrated circuit device is read out.

Isolating failing latches using a logic built-in self-test

Provided is a method for the collection and storage of information related to the operation of a chip module. The disclosed technology provides a chip data collection and storage controller. In one embodiment, a chip module is provided with a stand-alone memory that records information relevant to potential debugging operations. The stand-alone memory is on the same chip module as the chip die but is not part of the chip die. A data bus is provided between the chip module and the memory. In addition, the memory has I/O access so that information can be accessed in the event that the chip module cannot be accessed. Stored information includes, but is not limited to, environmental conditions, performance information, errors, time usage, run time, number of power on cycles, the highest temperature experience by the chip, wafer and x, y data, manufacturing info, FIR errors, and PRSO, SRAM PSRO values.

Information collection and storage for single core chips to 'N core chips

A virtual electronic fuse apparatus and methodology are disclosed that permit the state of an electronic fuse to change from an un-blown state to a blown state and then back to a virtual un-blown state. In one embodiment, the electronic fuse may change from the virtual un-blown state back to a virtual blown state.

Virtual electronic fuse apparatus and methodology

A virtual electronic fuse (VEF) apparatus and methodology are disclosed that permit the state of an electronic fuse to change from an un-blown state to a blown state and then back to a virtual un-blown state. In one embodiment, the electronic fuse may change from the virtual un-blown state back again to a virtual blown state. The fuse apparatus includes multiple VEFs, each VEF exhibiting a respective address. The fuse apparatus also includes an address pool including multiple address pool locations. A fuse programmer stores an address of one of the VEFs in one or more address pool locations to indicate one or more state changes for a particular VEF. The fuse programmer may also store different VEF addresses in different address pool locations to indicate state changes for different VEFs.

Growing community of inventors

Round Rock, TX, United States of America

Michael Wayne Harper