Dell Products Inc.

Michael Wayne Arms

Craig Lawrence Chaiken

Balasingh Ponraj Samuel

Vivek Viswanathan Iyer

Adolfo Sandor Montero

Anand Prakash Joshi

Justin L Frodsham

Ricardo Luis Martinez

Ibrahim Sayyed

Richard Martin Tonry

Vinod Makhija

Matthew G Page

Shubham Kumar

Stephen Cooper

Manjunath Gr

Dustin A Combs

Chun Yi (Jadis) Yang

Debasish Nath

Systems and methods for memory serviceability mitigation are described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: after failure of a memory device, notify a cloud service and enter a mitigation mode of operation with respect to the memory device, receive a message from the cloud service indicative of the provisioning of a replacement memory device, and, in response to the message and upon detection of a chassis intrusion event, leave the mitigation mode of operation with respect to the replacement memory device.

Systems and methods for memory serviceability mitigation

A method may include, during a PEI phase BIOS, responsive to a flag being set in a previous boot session of an information handling system to test a first designated region of a memory of the information handling system: testing the first designated region for a memory fault; in response to detecting the memory fault, mapping out the first designated region and designating an additional region of the memory as a designated region for SMRAM and repeating testing of additional designated regions, mapping out of failed additional designated regions, and designating new additional regions of the memory until a designated region passes testing without memory fault; and in response to detecting passage of testing without memory fault of a designated region comprising either of the first designated region or an additional region of the memory, configuring the designated region for use as the SMRAM for the information handling system.

Systems and methods for fault-resilient system management random access memory

Systems and methods are provided for supporting use of system BIOS components (e.g., such as BIOS debug messages, debugger firmware, UEFI drivers, etc.) that are stored separately from the remainder of system BIOS firmware for an information handling system. The system BIOS components may represent only a portion of the total BIOS firmware, and may be selectively retrieved and loaded from the separate storage into system memory when needed by the system BIOS for operating purposes (e.g., such as debugging operations).

Systems and methods for separate storage and use of system BIOS components

An information handling system may include at least one processor, a memory, and an embedded controller (EC). The information handling system may be configured to, prior to initialization of an operating system of the information handling system: execute memory reference code configured to test selected regions of the memory; transmit results of the memory reference code to the EC; store, at the EC, information indicative of respective likelihoods that particular regions of the memory are bad; and upon a subsequent boot, select a region of the memory having a low likelihood of being bad for loading a Basic Input/Output System (BIOS) of the information handling system.

Linking embedded controller with memory reference code and system bios shadowing

A system for secure processing of intra-processor data comprising firmware configured to operate on a processor. An operating system configured to operate on the processor. Payload configured to operate on the processor. An embedded controller coupled to the firmware, the operating system and the payload, wherein the embedded controller is configured to enable messaging between the firmware, the operating system and the payload.

System and method to securely exchange system diagnostics information between firmware, operating system and payload

A method may be provided in a basic input/output system embodied in persistent memory including two data areas for storing data associated with the basic input/output system and a code area comprising firmware for performing functionality of the basic input/output system. The method may include, at any given time, designating one of the data areas as a non-transitory data area and designating the other of the data areas as a transitory data area; and for each item of data associated with the basic input/output system, determining if such item of data is non-transitory-type data or transitory-type data, storing such item of data in the non-transitory data area if such item of data is determined to be non-transitory-type data, and storing such item of data in the transitory data area if such item of data is determined to be transitory-type data.

Shared transient memory storage in basic input/output system environment

Embodiments of information handling systems (HSs) and computer-implemented methods are provided herein to detect and recover from spurious PCIe device resets. One embodiment of a disclosed method is performed by a host processor of an IHS that includes a plurality of Peripheral Component Interconnect Express (PCIe) devices, each including a set of PCIe configuration registers containing configuration settings for the PCIe device. The disclosed method includes generating, in response to the IHS transitioning from a lower power state to a higher power state, a PCIe device table containing the configuration settings stored within the set of PCIe configuration registers for each of the PCIe devices; determining, in response to detecting a system management interrupt (SMI), whether or not a spurious reset has occurred for at least one of the PCIe devices; and recovering the at least one PCIe device if said determining indicates that a spurious reset has occurred for the at least one PCIe device.

Information handling system and method to detect and recover from spurious resets of PCIe devices

Information handling systems (IHS) and methods are provided to automatically synchronize operating system (OS) and boot firmware languages. In one embodiment, a method may detect a change in an active OS language from a first language pack to a second language pack, notify the boot firmware that the active OS language was changed, and provide an identity of the second language pack to the boot firmware during OS runtime. When the IHS is subsequently rebooted, the active boot firmware language may be synchronized to the active OS language. In another embodiment, the method may detect a change in an active boot firmware language from a first language pack to a second language pack, notify the OS that the active boot firmware language was changed, and provide an identity of the second language pack to the OS during a pre-boot phase. When the OS is subsequently booted, the active OS language may be synchronized to the active boot firmware language.

Information handling system and method to automatically synchronize operating system and boot firmware languages

A method includes invoking, by an embedded controller at an information handling system, a test procedure to evaluate functionality of motherboard resources at the information handling system. A result of the test procedure is displayed at a primary display device using a built in self test function incorporated at the primary display device.

Method and apparatus for identifying and reporting faults at an information handling system

Embodiments of information handling systems (IHSs) and methods are provided herein to automatically detect and recover from boot failures, such as no power failures and no POST failures, without suffering the information loss that typically occurs in conventional recovery methods. One embodiment of an IHS disclosed herein includes a system real-time clock (RTC) configured to maintain current date and time values, a host processor configured to execute boot firmware and perform a Power-On Self-Test (POST) during a boot process for the IHS, and an embedded controller (EC) configured to execute embedded controller firmware during the boot process to detect a no power failure or a no POST failure, and reset or remove power from the system RTC if a no power failure or a no POST failure is detected.

Information handling system and method to detect and recover from no power/no post failures

Systems and methods are provided for creating and/or modifying memory configuration settings (e.g., such as memory timing and memory drive voltage) for use at selected and/or varying memory temperature/s. The disclosed systems and methods may be implemented to create a relationship between optimized memory configuration settings for different memory temperatures during burn-in testing and/or on an ad-hoc basis.

Systems and methods for creating and/or modifying memory configuration settings

Embodiments of information handling systems (IHSs) and methods are provided herein to dynamically detect and recover from thermally induced memory failures. Some embodiments include receiving an interrupt corresponding to a memory failure, detecting a current temperature of one or more memory components, and performing a series of memory tests on a specific block of memory within the memory components if the current temperature exceeds a maximum operating temperature specified for the memory components. Some embodiments include storing original contents of the specific block of memory within another memory component of the IHS, performing a first memory test on the specific block of memory at the current temperature, subsequently performing a second memory test on the specific block of memory at a temperature significantly lower than the current temperature, and determining that the memory failure is a thermally induced memory failure if the first memory test fails and the second memory test passes.

Information handling system and method to dynamically detect and recover from thermally induced memory failures

An information handling system operating an automated UEFI variable update management system may comprise a processor executing machine-readable executable code instructions of the automated UEFI variable update management system to save to a memory and execute a first plurality of UEFI variables included in a first terse executable image, to receive a second terse executable image including a second plurality of UEFI variables in a second preset order, wherein each of the first plurality of UEFI variables and the second plurality of UEFI variables including a variable value, and a variable key pointing to a variable value location in the memory, to compare the first plurality of UEFI variables to the second plurality of UEFI variables, to retrieve from the first terse executable image and store in a variable update map the first plurality of UEFI variables, to retrieve from the second terse executable image and store in the variable update map the second plurality of UEFI variables, and to store the variable update map to the memory.

System and method for automatically managing updated UEFI variables

Systems and methods are provided that may be implemented to hide operating system kernel data in system management mode memory. An information handling system includes a system memory, central processing unit (CPU), and Basic Input Output System (BIOS). The CPU is operable in a system management mode and is programmable to specify an SMM region of the system memory that is only accessible when the CPU is operating in the SMM. The BIOS is programmed to save kernel data from a non-SMM region of the system memory to the SMM region and then clear the kernel data from the non-SMM region in response to an operating system (OS) generating a system management interrupt (SMI) and to restore the kernel data to the non-SMM region of the system memory from the SMM region in response to the OS generating a SMI.

Systems and methods for hiding operating system kernel data in system management mode memory to thwart user mode side-channel attacks

A method performed by an information handling system, the method including bifurcating, by a processor of the information handling system, an I/O unit (IO unit) of the information handling system into a first root port and a second root port, wherein the first root port comprises a first pre-determined number of first lanes of the IO unit and the second root port comprises the first pre-determined number of second lanes of the IO unit. The method further including discovering, by the processor, a first I/O device (IO device) coupled to the IO unit, wherein the first IO device utilizes a first lane width that is greater than the first pre-determined number of lanes, and in response to discovering the first IO device, bifurcating, by the processor, the IO unit into a third root port, wherein the third root port comprises the first lanes and the second lanes.

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Pflugerville, TX, United States of America

Michael Wayne Arms