Intel Corporation

Michael Walk

Yuan-Liang Li

David Gregory Figueroa

Thomas Dory

Boyd L Coomer

Robert L Sankman

Jianqi He

John Stephen Guzek

Jiangqi He

Kishore K Chakravorty

Charan K Gurumurthy

Jorge Pedro Rodriguez

Brent S Stone

Hamid Azimi

Huong T Do

Toshimi Kohmura

Joan K Vrtis

Aaron Dean Hale

A package includes at least one electronic component mounted on an imprinted substrate. In an embodiment, the substrate may comprise conductive traces, vias, and patterns of lands on one or more layers. Such features may be formed by imprinting in one operation rather than sequentially. Conductor features, such as trenches, holes, and planes, may be formed of different sizes simultaneously. One or more vias may be formed in one or more trenches. Methods of fabricating an imprinted substrate, as well as application of the imprinted package to an electronic assembly, are also described.

Methods for manufacturing imprinted substrates

A package includes at least one electronic component mounted on a substrate formed through imprinting. In an embodiment, the substrate may comprise conductive traces, vias, and patterns of lands on one or more layers. Conductor features of different geometries may be formed by imprinting them simultaneously on one or both surfaces of an imprintable tape. Fabrication apparatus and methods, as well as application of the imprinted package to an electronic assembly, are also described.

Substrate-imprinting methods

A circuit package may include an upper surface of first conductive elements and second conductive elements. The first conductive elements may receive input/output signals from respective conductive elements of an integrated circuit die, and the second conductive elements may receive a first plurality of the input/output signals from respective ones of the first conductive elements. A lower surface of the package may include third conductive elements, the third conductive elements to receive a second plurality of the input/output signals from respective other ones of the first conductive elements.

I/O Architecture for integrated circuit package

Electronic packages and components thereof formed by substrate-imprinting

An article of manufacture and system, as well as fabrication methods therefore, may include a plurality of lands disposed on a surface of a substrate wherein the lands are oriented at an angle to the surface of the substrate and further wherein the substrate is formed of conductive layers that are formed such that a non-conductive layer does not interpose between the conductive layers and their coupling.

Device and method for tilted land grid array interconnects on a coreless substrate package

I/O architecture for integrated circuit package

Adhesive material is applied to a surface of a metallic core layer. The adhesive material is removed from a conductive region of the metallic core layer. A metallic contact is provided over the conductive region of the metallic core layer. The metallic core layer is laminated to an imprinted buildup layer, the buildup layer having a dielectric region and a conductive region, wherein a nonconductive region of the metallic core layer is bonded to the dielectric region of the buildup layer and the conductive region of the metallic core layer is bonded to the conductive region of the imprinted-buildup layer.

Multi-layer integrated circuit package

A electrical interface for an electronic package, using lands on the package which are non-planar with metal layers within the package. This non-planar or tilted land grid array (TLGA) package is assembled with a complementary TLGA socket to make electronic connection to the package.

Tilted land grid array package and socket, systems, and methods

Numerous embodiments of a method and apparatus for forming an imprinting tool are disclosed. In one embodiment, a method of forming an imprinting tool comprises forming a first mold by use of one or more printing processes, forming a second mold from the first mold, and forming an imprinting tool from the second mold, where the imprinting tool is formed at least in part by metalizing at least a portion of the second mold.

Methods for forming an imprinting tool

A system may include a coreless substrate, a layer of material attached to the substrate, the layer of material having a lower elastic modulus than the substrate, an interposer coupled to the layer of material, and a capacitive layer coupled to the interposer.

Integrated circuit package with low modulus layer and capacitor/interposer

A capacitor (FIGS. ) includes one or more extended surface lands ( , FIGS. ). In one embodiment, each extended surface land is a land on a top or bottom surface of the capacitor, having a land length that is equal to at least 30% of the width ( , FIG. ) of the capacitor or 20% of the length ( , FIG. ) of the capacitor. When embedded within an integrated circuit package ( , FIG. ), two or more vias ( ) can be electrically connected to the extended surface lands ( ).

Capacitor with extended surface lands and method of fabrication therefor

A thin film capacitor provides an interposer substrate between an integrated circuit die and an organic substrate. The interposer substrate includes a first conductive layer deposited on a base substrate layer. A portion of the first conductive layer provides a first electrode region serving as a first plate of the capacitor. Portions of a second conductive layer forming a second electrode region serving as a second plate of the capacitor. A dielectric layer is disposed between the first and second conductive layers to provide for capacitive regions between the first electrode region and the second electrode region. The base substrate layer and die may be based on similar semiconductor materials, such as Silicon or Gallium Arsenide, to provide an improved coefficient of thermal expansion match.

Interposer substrate with low inductance capacitive paths

An electronic package ( , FIG. ) includes one or more capacitors ( ) embedded within one or more layers ( ) of the package. The embedded capacitors are discrete devices, such as integrated circuit capacitors (FIGS. ) or ceramic capacitors. During the package build-up process, the capacitors are mounted ( , FIG. ) to a package layer, and a non-conductive layer is applied ( ) over the capacitors. When the build-up process is completed, the capacitor's terminals ( , FIG. ) are electrically connected to the top surface of the package. The embedded capacitor structure can be used in an integrated circuit package ( , FIG. ), an interposer ( ), and/or a printed circuit board ( ).

Growing community of inventors

Mesa, AZ, United States of America

Michael Walk