Hrl Laboratories, LLC

Hughes Aircraft Company

Other

The Boeing Company

United States of America As Represented by the Secretary of the Air Force

Hughes Electronics Corporation

Michael W Yung

Donald A Hitko

Daniel Yap

Carson R White

Jose Cruz-Albrecht

Narayan Srinivasa

Joseph S Colburn

Albert E Cosand

Zhiwei A Xu

Michael J Little

Hugh L Garvin

David S Matthews

Susan L Morton

James A Foschaar

Jason W May

Michael L Campbell

Soyeon P Laub

A convolution circuit includes: a plurality of input oscillators, each configured to: receive a corresponding analog input signal of a plurality of analog input signals; and output a corresponding spiking signal of a plurality of spiking signals, the corresponding spiking signal having a spiking rate in accordance with a magnitude of the corresponding analog input signal; a plurality of 1-bit DACs, each of the 1-bit DACs being configured to: receive the corresponding spiking signal of the plurality of spiking signals from a corresponding one of the input oscillators; and receive a corresponding weight of a convolution kernel comprising a plurality of weights; output a corresponding weighted output of a plurality of weighted outputs in accordance with the corresponding spiking signal and the corresponding weight; and an output oscillator configured to generate an output spike signal in accordance with the plurality of weighted outputs from the plurality of 1-bit DACs.

Spike domain convolution circuit

An automatic tuning circuit for matching an antenna to a radio receiver. The automatic tuning circuit includes a tunable non-Foster circuit for coupling the receiver and the antenna; and sensing and feedback circuits for sensing the combined capacitance of the tunable non-Foster circuit and the antenna and for tuning the tunable non-Foster circuit to automatically minimize the combined capacitance of the tunable non-Foster circuit and the antenna.

Wide bandwidth automatic tuning circuit

A method of and circuit for improving stabilization of a non-Foster circuit. The method comprises steps of and the circuit includes means for measuring a noise hump power at an antenna port or an output port of the non-Foster circuit, comparing the measured noise hump power with a desired level of noise power that corresponds to a desired operating state of the non-Foster circuit, and tuning the non-Foster circuit to generate the desired level of noise power to achieve the desired operating state of the non-Foster circuit.

Non-foster circuit stabilization method

A spike domain asynchronous neuron circuit includes a first spike to exponential circuit for emulating kinetic dynamics at a neuron input and converting voltage spikes into exponentials, a first adjustable gain circuit for emulating homeostatic plasticity coupled to the first voltage-type spike exponential output and having a first current output, a neuron core circuit coupled to the first current output for emulating a neuron core and having a spike encoded voltage output, a filter and comparator circuit coupled to the spike encoded voltage output and having a gain control output coupled to the first adjustable gain circuit for controlling a gain of the first adjustable gain circuit, and an adjustable delay circuit for emulating an axonal delay coupled to the spike encoded voltage output and having an axonal delay output.

Spike domain neuron circuit with programmable kinetic dynamic, homeostatic plasticity and axonal delays

A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as 'non-Foster circuits.' The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).

Differential negative impedance converters and inverters with variable or tunable conversion ratios

A delay circuit includes a first flip flop (FF), a transistor connected to the FF, a first resistor capacitor circuit (RCC) coupled to the transistor and between a voltage and a ground, a first comparator for comparing an output of the first RCC and a voltage reference, gate logic coupled to the input line and to an output of the first FF and to a second FF, a second transistor coupled to the second FF, a second RCC coupled to the second transistor and between the voltage and ground, a second comparator for comparing an output of the second RCC and the voltage reference and coupled to the first FF, and output logic coupled to the first and second comparators.

Analog pulse delay circuit with multiple output potential

A non-Foster impedance power amplifier has a current amplifying device coupled in either an emitter-follower or source-follower configuration with a reactive load such as an antenna load. A negative impedance circuit is provided upstream of a gate or base or other control element of said current amplifying device.

Non-foster impedance power amplifier

A communication receiver () includes a data receiver () that receives a pulse-position modulated signal (). A clock circuit () separates a reference clock signal () into multiple coordinating clock signals A, B, and C. Multiple time integrators () are gated to generate multiple time-integrated signals in response to the pulse-position modulated signal () and the coordinating clock signals A, B, and C. A combiner () forms a demodulated signal from the time-integrated signals IntA, IntB, and IntC.

PPM receiving system and method using time-interleaved integrators

Optical bond-wire interconnections between microelectronic chips, wherein optical wires are bonded onto microelectronic chips. Such optical connections offer numerous advantages compared to traditional electrical connections. Among other things, these interconnections are insensitive to electromagnetic interference and need not be located at the edges of a chip but rather can be placed for optimal utility to the circuit function. In addition, such interconnections can be given the same or other pre-specified lengths regardless of the placement in the module and they are capable of signal bandwidths up to 20 Gigahertz without causing a cross-talk problem. A method of fabrication of such optical interconnections using optical fiber, a laser or photodetector and etched mirror and etched V-shaped grooves.

Optical bond-wire interconnections and a method for fabrication thereof

A method for fabricating resilient z-axis contacts to electrically interconnect IC wafers or MCMs in 3-D integrated circuits uses photolithography to provide larger carrier sizes, higher contact densities by decreasing the spacing, smaller contact footpads, and precise control of the contact's shape and position. The contacts are fabricated by forming photoresist patterns on the carrier's top and bottom surfaces that are initially rectangular, and then reflowing the photoresist materials to provide smooth surfaces suitable for forming the metal contacts, and depositing metal layers over the respective patterns. Second photoresist patterns are formed over respective metal layers to conform with the contact's shape, the metal is etched away according to the pattern, and the photoresists are removed such that the remaining metalization forms a resilient z-axis contact that is attached to the carrier and extends therefrom with a predetermined shape.

Method for fabricating resilient z-axis contacts for electrically

A system (30) and method is provided for enumerating acyclic paths in an information processing system. The system (30) incorporates multiple processor nodes (18) or functional units interconnected by point-to-point links (20). The hardware of the information processor is represented as a mixed graph with graph nodes (32) for processors and with graph edges (34) representing communication links (20). All the useful paths from the source nodes of the data to the destination nodes of the data are determined in accordance with the system and method of the present invention. These paths are then stored as a list in a table indexed by the source and destination nodes. Thus, when the need for a interprocessor communication path arises, the table can be consulted to find a permissible path. The system (30) efficiently performs interprocessor communication routing and can be utilized in real time.

System and method for enumerating all acyclic paths in a processing

Short circuits in the power distribution network of a circuit structure are accurately located and isolated by providing selected power distribution lines with areas whose width is reduced sufficiently to produce a highly resolved current-induced hot spot in response to a downstream short circuit. The invention is particularly applicable to crossovers of power distribution lines separated by an insulating layer. The upper line is divided into a plurality of spaced parallel channels in the crossover vicinity. The channels each include areas of further reduced width at their opposite ends, preferably outside of but proximate to the crossover area, where the hot spots are formed. A short circuit on any of the channels is isolated by cutting at the areas of further reduced width on either side of the fault. Terminal lines of the power distribution network can also be provided with areas of reduced width proximate to the global power distribution line from which they are supplied; these areas form a hot spot in response to a short circuit on the terminal line, and can be cut to isolate the terminal line. Low level faults can be detected with a high degree of resolution and very small space requirements.

Defect tolerant power distribution network and method for integrated

An array of processing element nodes are provided on a semiconductor wafer. A mixed redundancy approach is preferably employed wherein two spare core logic circuit modules 52, 58 are available for use at each node. Each spare core logic module can be connected to one of four different nodes. An H-net 94 interconnects adjacent nodes in such manner that faults in the circuit modules can be easily tested and repaired.

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Los Angeles, CA, United States of America

Michael W Yung