Ramtron International Corporation

Hitachi, Ltd.

United Technologies Corporation

Racom Systems, Inc.

Other

Michael W Yeager

Yoshihiko Yasu

Hiroyuki Sakai

Gary T Carroll

Dennis R Wilson

J Donald Pauley

Donald J Verhaeghe

Gregory M Smith

Jeffery E Downs

Roger G Cox

Mark A Reber

Lance Leslie Flake

A sports simulation robot for playing games and drills on a standard court or field during which the robot will simulate the competitive play of a human opponent with specific playing characteristics such as strategy, physicality, playing style and skill level. The robot is small enough and light enough to be easily stored, transported and deployed; has a ball storage device for retrieving, storing and dispensing the balls; can reload the balls into the ball storage device by catching them or by autonomously reloading them; has a ball firing system that is compact, lightweight and efficient, that can generate the shot dynamics that the corresponding human opponent would be capable of generating; has a drive system that makes it capable of moving around the court at speeds that are comparable to the speed of the human opponent that is being simulated; has the ability to call shots In or Out, keep the score, provide coaching, and keeps a record over time of the player's performance against different categories of simulated opponents.

Personal sports simulation robot

A semiconductor memory device, divided into plural blocks, comprising: a memory array having a non-volatile memory element which makes the read cycle and the write cycle to be substantially equivalent; plural storage elements storing the information of write protection/permission corresponding to each said block respectively; and a setting circuit to set the information of write protection/permission to said plural storage elements, wherein said setting circuit sets the write-protection information to said plural storage elements at the write cycle after designated plural read cycles. Therefore, the write protection/permission can be set by the unit of block, block by block, so that the write-protected ROM and the RAM can be set freely. Furthermore, the complexity of the setting procedure of write protection/permission may prevent the accidental false setting caused by a system runaway and so forth.

Write Protection for a non-volatile memory

An integrated circuit capacitor and method for making the same utilizes a ferroelectric dielectric, such as lead-zirconate-titanate ('PZT'), to produce a high value peripheral capacitor for integration on a common substrate with a ferroelectric memory array also utilizing ferroelectric memory cell capacitors as non-volatile storage elements. The peripheral capacitor is linearly operated in a single direction and may be readily integrated to provide capacitance values on the order of 1-10 nF or more utilizing the same processing steps as are utilized to produce the alternately polarizable memory cell capacitors. The high value peripheral capacitor has application, for example, as a filter capacitor associated with the on-board power supply of a passive radio frequency ('RF') identification ('ID') transponder.

Method of making integration of high value capacitor with ferroelectric

A semiconductor memory device, divided into plural blocks, includes a memory array having a non-volatile memory element in which address access times for the read cycle and the write cycle are substantially equivalent to one another (for example, a ferroelectric memory element). Plural storage elements stores the information for write protection/permission corresponding to each of the blocks, respectively. A setting circuit is provided to set the information for write protection/permission to the plural storage elements. The setting circuit sets the write-protection information to the plural storage elements at the write cycle after designated plural read cycles. Therefore, the write protection/permission can be set in block units block by block, so that the write-protected areas for a ROM and a RAM formed by the non-volatile memory element can be set freely. Furthermore, the complexity of the setting procedure for write protection/permission serves to prevent accidental false setting caused by system runaway or the like.

Semiconductor memory device

A system and method for selective write protection for a non-volatile memory device which comprises a superset of the existing JEDEC 21-C standard and in which user definable portions of a non-volatile memory device can be write protected instead of only the entire device. The write-protection technique of the present invention can be selectably enabled or disabled dynamically as determined by a user. Moreover, the system and method of the present invention provides for storage of the device write-protection configuration in non-volatile memory in order that the device can be restored to its last known write-protection state in the event it is powered down or the current configuration is otherwise lost.

Sysyem and method providing selective write protection for individual

Integration of high value capacitor with ferroelectric memory

An integrated FSK detector circuit includes a first counter that receives a carrier signal and provides a multiple-bit output for reducing the frequency of the carrier signal into a plurality of weighted sub-multiples. An oscillator enable decoder circuit provides predetermined calibrate and measure pulses in response to the first counter output. A gated oscillator receives the calibrate and measure pulses and provides a burst of oscillator pulses during these time intervals. A second counter has an input coupled to the output of the gated oscillator and an up/down control terminal coupled to the output of the first counter. The output of the second counter also provides a multiple-bit output for reducing the frequency of the gated oscillator pulses. An FSK decoder logic circuit decodes the multiple-bit output of the second counter into a single bit FSK detect signal. The FSK detector circuit also includes a reset circuit coupled to the first counter for resetting between FSK detections.

Method and apparatus for detecting an FSK encoded carrier signal

A power supply self-contained within a portable RF/ID transponder includes a full wave rectifier having an input for receiving an antenna signal and outputs for providing power supply and ground voltages, wherein the power supply voltage has a time varying voltage waveform corresponding to the electric field generated by a reader/controller. The power supply further includes a clamping circuit for regulating the power supply voltage and a ferroelectric filter/storage capacitor coupled between the power supply and ground outputs of the full wave rectifier. The power supply further includes a power enable circuit for constantly monitoring the supply voltage waveform and for providing a power enable indication after an initial portion of the supply voltage waveform rises above a predetermined power-up threshold level and for removing the power enable indication when a terminal portion of the supply voltage waveform falls below a predetermined power-down level. The power-up and power-down thresholds describe a proper voltage range of operation for the ferroelectric memory in the transponder. The power enable indication is provided to the ferroelectric memory so that the memory is only operated when the power supply voltage is within the proper range so that data is valid during read and write operations.

Power supply and power enable circuit for an RF/ID transponder

A system and method wherein a predetermined soft fuse value may be written to a corresponding soft fuse register to control subsequent access to a number of lock bits in a non-volatile semiconductor memory array which are provided for selectively precluding writes to predetermined portions of the memory array. In a specific embodiment, the system and method may be utilized in conjunction with radio frequency ('RF') identification ('ID') transponders incorporating a non-volatile ferroelectric random access memory ('FRAM') array integrated circuit.

System and method for write-protecting predetermined portions of a

An intermediate storage register is added to the combinational logic of an accumulator and is located so that a second term may be stored in the first half of an adder array, while a first term continues the accumulation process in the second half of the array.

Accumulator for complex numbers

A pipelined arithmetic processor includes a pair of multipliers in parallel feeding an ALU that, in turn, feeds a pair of parallel accumulators, the various sections being connected by controllable data paths and controlled by a set of pipelined registers feeding a series of decoders.

Growing community of inventors

Colorado Springs, CO, United States of America

Michael W Yeager