Intel Corporation

Michael W Williams

James M Dodd

John B Halbert

Kuljit Singh Bains

Robert N Murdoch

Andrew M Volk

David Zimmerman

Narendra S Khandekar

Robert J Riesenman

Howard S David

Randy M Bonella

David J McDonnell

Jasmin Ajanovic

Blaise B Fanning

Robert J Royer, Jr

Jeffrey R Wilcox

Eng Hun Ooi

Puthiya K Nizar

Dennis W Brzezinski

Ritesh B Trivedi

Robert M Ellis

Chris B Freeman

Jim M Dodd

Mikal Hunsaker

Pete D Vogt

Hing Yan To

Joseph H Salmon

William Dawson Kesling

Sathyamurthi Sadhasivan

Lloyd L Pollard, Ii

Chung Lam

Nitin B Gupte

Samuel D Benn

In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

Non-volatile memory interface

According to some embodiments, a method and apparatus are provided to receive a first data burst associated with a first data line and a second data burst associated with a second data line, determine a first one or more stuff bits to be transmitted after the first data burst and a second one or more stuff bits to be transmitted after the second data burst, and output data comprising the first data burst and the first one or more stuff bits and the second data burst and the second one or more stuff bits.

Stuffing bits on a memory bus between data bursts

A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.

Method and system for error management in a memory device

Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.

Low speed access to DRAM

Embodiments of the invention are generally directed to systems, methods, and apparatuses to save dynamic random access memory (DRAM) self-refresh power. In some embodiments, the refresh frequency of a DRAM is reduced and errors are allowed to occur. In error check mode, the DRAM stores data and corresponding error check bits. The error check bits may be used to scrub the memory and fix the errors.

Systems, methods, and apparatuses to save memory self-refresh power

Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.

Memory buffer device integrating refresh logic

Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.

Buffered memory module with implicit to explicit memory command expansion

An apparatus and a method to track command signal occurrence for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes an interface to couple to a data bus, the data bus to transfer data between the interface and one or more memory devices, and a logic unit to generate a command occurrence signal to identify when a command signal is issued, wherein a set of data transfer operations on one of the one or more memory devices are completed in response to the command occurrence signal, a transition of a flag signal, and a chip select signal corresponding to the one memory device. Other embodiments have been claimed and described.

Apparatus and method to track command signal occurrence for DRAM data transfer

A method and an apparatus to track transition of a flag signal for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes one or more memory devices, coupled to a data bus, to receive a command signal, wherein the command signal initiates a set of data transfer operations to transfer data between the data bus and one of the one or more memory devices; and a timing unit, coupled to the one or more memory devices, to receive the command signal, a flag signal, and a memory select signal, the timing unit to generate a trigger signal, in response to a transition of the flag signal, to complete the data transfer operations if the memory select signal corresponds to the one of the one or more memory devices. Other embodiments have been claimed and described.

Apparatus and method to track flag transitions for DRAM data transfer

A memory controller or other device may be programmed with a data mask mapping scheme. A selection device within the memory controller may be set with the data mask mapping scheme between data and a data mask. In one embodiment, a storage device may be included and programmed with the data mask mapping scheme.

Mapping data masks in hardware by controller programming

A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.

Obtaining data mask mapping information

Growing community of inventors

Citrus Heights, CA, United States of America

Michael W Williams