Sun Microsystems, Inc.

Oracle International Corporation

Michael W Parkin

Ashley N Saulsbury

Earl T Cohen

David R Emberson

Thomas M McWilliams

Derek E Pappas

Liang T Chen

Jeffrey B Rubin

Nyles I Nettleton

Jeffrey M Broughton

Daniel S Rice

Ihao Chen

William Kwei-Cheung Lam

Andreas G Nowatzyk

Oyekunle A Olukotun

Robert Cypher

James B Burr

David S Allison

Ankur Narang

Michael S Ball

Charles T Cheng

A method and apparatus for generating logical frames from arbitrating among packets is disclosed. An integrated circuit (IC) includes an arbitration circuit configured to generate a logical frame having a first number of bytes by selecting at least one a plurality of packets received from different functional circuit blocks. At least one of the plurality of packets is of a different data size than at least one other one of the plurality of packets. The arbitration circuit is configured to, when selecting two or more of the plurality of packets, generate the logical frame by concatenating selected packets together. The IC further includes a framing circuit configured to generate, based on the logical frame, a physical frame for an outgoing transmission over a serial communications link, wherein the physical frame comprises a second number of bytes that is less than or equal to the first number of bytes.

Arbiter for logical to physical frame conversion

A method and apparatus for logical-physical frame conversion in a serial link application is disclosed. An integrated circuit (IC) includes a serializer-deserializer (SERDES) coupled to a communications link and configured to convert outgoing data transmissions from parallel to serial and convert incoming data transmissions from serial to parallel. A framing unit is coupled to the SERDES and configured to convert data between a logical frame format for parallel transfer and a physical frame format for serial transfer over the communications link. The logical frame has a first number of bytes and the physical frame has a second number of bytes less than or equal to the first number. The first number is variable and the second number is fixed. The framing unit is further configured to convert data between the logical frame format and the physical frame format when the first number is a non-integral power of two.

Method and apparatus for conversion between logical and physical frames for a serial link application

A memory controller, system, and methods are disclosed. The system comprises a memory controller interconnected to a plurality of memory chips. Each memory chip stores data at a plurality of locations. The memory controller performs a sparing transaction comprising reading data from a given location of one or more of the memory chips including a first memory chip, writing the data to a given location of one or more of the memory chips including a second memory chip, wherein during writing, data from the first memory chip is written to the second memory chip, and allowing additional memory transactions directed to the memory chips between the start of reading and the end of writing unless the additional memory transaction is targeted to the given location. In a further embodiment, the sparing transaction comprises correcting errors in the data before writing the data.

Data corruption avoidance in DRAM chip sparing

A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate form to an executable form.

Method and apparatus for simulation system compiler

According to the invention, a processing core () comprising a processing pipeline () having N-number of processing paths (), each of which process instructions () on M-bit data words. In addition, the processing core () includes one or more register files (), each preferably having Q-number of registers which are M-bits wide. Preferably, one of the Q-number of registers in at least one of the register files () is a program counter register dedicated to hold a program counter, and one of the Q-number of registers in at least one of the register files is a zero register dedicated to hold a zero value. In this manner, program jumps can be executed by adding values to the program counter in the program counter register, and memory address values can be calculated by adding values to the program counter stored in the program counter register or to the zero value stored in the zero register.

VLIW computer processing architecture having the problem counter stored in a register file register

A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.

Method and apparatus for simulation processor

A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.

Method and apparatus for cycle-based computation

A processing core comprising R-number of processing pipelines each comprising N-number of processing paths. Each of the R-number of processing pipelines are synchronized together to operate as a single very long instruction word (VLIW) processing core. The VLIW processing core is configured to process R&#xd7;N-number of VLIW sub-instructions in parallel. In addition, the R-number of pipelines can be configured to operate independently as separately operating pipelines. In accordance with one embodiment of the present invention, each of the R-number of processing pipelines comprises S-number of register files, such that the processing core comprises R&#xd7;S-number of register files. In accordance with another embodiment of the present invention, each of the R-number of processing pipelines comprises one register file for every two of the N-number of processing paths, such that S=N/2. In accordance with yet another embodiment of the invention, a single VLIW processing instruction comprises R&#xd7;N-number of P-bit sub-instructions appended together.

Computer processing architecture having a scalable number of processing paths and pipelines

According to the invention, a processing core is disclosed. The processing core includes one or more processing pipelines and a number of register flies. The processing pipelines having a total of N-number of processing paths, where each of the processing paths processes instructions on M-bit data words. Each of the number of register files has Q-number of registers that are each M-bits wide. The Q-number of registers within each of the plurality of register files are either private or global registers. When a value is written to one of said Q-number of said registers, which is a global register within one of said number of register files, the value is propagated to a corresponding global register in the other of the number of register files. When a value is written to one of said Q-number of the registers, which is a private register within one of said number of register files, the value is not propagated to a corresponding register in the other of said number of register files.

VLIW computer processing architecture having a scalable number of register files

A temporal delay circuit for synchronizing a source synchronous input with a local clock is provided. The source synchronous input comprises a data input and a source synchronous clock. The temporal delay circuit includes a temporal delay queue, a write pointer arranged to write the data input to the temporal delay queue based on the source synchronous clock, and a read pointer synchronized with the local clock and arranged to read from the temporal delay queue according to a desired delay.

Source synchronous I/O using temporal delay queues

A novel processor chip ( ) having a processing core ( ), at least one bank of memory ( ), an I/O link ( ) configured to communicate with other like processor chips or compatible I/O devices, a memory controller ( ) in electrical communication with processing core ( ) and memory ( ), and a distributed shared memory controller ( ) in electrical communication with memory controller ( ) and I/O link ( ). Distributed shared memory controller ( ) is configured to control the exchange of data between processor chip ( ) and the other processor chips or I/O devices. In addition, memory controller ( ) is configured to receive memory requests from processing core ( ) and distributed shared memory controller ( ) and process the memory request with memory ( ). Processor chip ( ) may further comprise an external memory interface ( ) in electrical communication with memory controller ( ). External memory interface ( ) is configured to connect processor chip ( ) with external memory, such as DRAM. Memory controller ( ) is configured to receive memory requests from processing core ( ) and distributed shared memory controller ( ), determine whether the memory requests are directed to memory ( ) on chip ( ) or the external memory, and process the memory requests with memory ( ) on processor chip ( ) or with the external memory through external memory interface ( ).

VLIW computer processing architecture with on-chip dynamic RAM

An interconnect controller for use in an arbitrary topology collection of nodes in a network suitable for use for both data sharing and distributed computing. The interconnect controller provides four (4) serial ports and two (2) parallel ports for communicating with adjacent nodes in a network. Linked ports between two nodes provide a continuous stream of information with idle packets filling non-data transfer cases. The logic of the interconnect controller provides for adaptive routing and to topology independence and allows for the sharing of a common clock for synchronizing the packet transmission.

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Palo Alto, CA, United States of America

Michael W Parkin