Apple Inc.

Apple Ii 'c.

Michael W Murphy

Paul A Baker

William P Cornelius

Brett W Degner

Colin Whitby-Strevens

Joshua P De Cesare

Keith E Diefendorff

Timothy R Paaske

Eric Werner Anderson

David Ferguson

Corey N Axelowitz

Ron Hochsprung

John T Orchard

James E Zmuda

Mark P Colosky

Eric C Gaertner

Jangwon Lee

Ronald P Songco

Peter Louis Bielawski

Kevin C Gotze

Ian P Shaeffer

Niel David Warren

Matthew Xavier Mora

Hardik K Doshi

Brett D George

Raymond B Montagne

Girault W Jones, Jr

Gopal Thirumalai Narayanan

Sreenivas Tallam

Ian P Schaeffer

Andre M Glover

Deepak K Mishra

Matthew X Mora

Girault Jones

Various techniques related to authenticating and verifying the integrity of data received by a computer system from an external source (such as a sensor) are disclosed. Hardware circuits are disclosed that, along with the computer processor, allow for error-checking and authentication of data received by the computer system. For instance, the hardware circuits may generate a separate authentication code that can be compared to the authentication code in the data itself to determine whether or not the message is authentic and whether or not there is an error in the data. The disclosed techniques reduce the processing requirements of a computer system and can be implemented using simple hardware circuit designs.

Scheme for transferring and authenticating data

A computer includes a processor, a PCIe-compatible interface bus that includes a root that is connected to the processor, and a routing complex that is connected to the root and is controlled by the processor. The computer also includes a first interface slot that is connectable to the root by the switches, a second interface slot that is connectable to the root by the switches, and an extended interface slot that is connectable to the root by the switches. The switches are configured based on properties of a first peripheral device to define a first switching configuration when the first peripheral device is connected only to the first interface slot and to define a second switching configuration when the first peripheral device is connected to both of the first interface slot and the extended interface slot.

Interface bus resource allocation

A method and apparatus of a device that load balances a first plurality of Peripheral Connect Interconnect ports is described. In an exemplary embodiment, the device detects a second plurality of PCI ports in the device. In addition, the device determines a load for each port in the first and second plurality of PCI ports and sorts the second plurality of PCI ports. The device further load balances the first plurality of PCI ports using at least a PCIe switch and the load determination of the second plurality of PCI ports. The device additionally communicates data between the first and second plurality of PCI ports.

Systems and methods for PCI load balancing

Methods and apparatus for augmenting routing resources. In one exemplary embodiment, a Thunderbolt&#x2122; transceiver incorporates a Peripheral Component Interconnect Express (PCIe) bus that supports hot-plugging and hot-unplugging of peripheral devices. Unfortunately, for various backward compatibility reasons, existing PCIe bus enumeration protocols can quickly exhaust the PCIe routing resources (for example, PCIe bus numbers) resulting in undesirable consequences (for example, crashes, dead connections, etc.) The present disclosure describes schemes for augmenting the pool of PCIe bus numbers and dynamically re-assigning PCIe bus numbers, so as to eliminate the aforementioned concerns.

Methods and apparatus for augmented bus numbering

A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.

Reducing latency in a peripheral component interconnect express link

The disclosed embodiments provide a system that facilitates use of a network of components in a computer system. The system includes a bandwidth-allocation apparatus that provides a write transaction limit for a component on the network. The system also includes a transaction-management apparatus that compares the write transaction limit to a set of outstanding write transactions for the component upon detecting a write transaction from the component to the network. If the write transaction causes the set of outstanding write transactions to exceed the write transaction limit, the transaction-management apparatus restricts transmission of the write transaction over the network.

Limiting bandwidth for write transactions across networks of components in computer systems

Methods and apparatus for efficiently transporting data through network tunnels. In one embodiment, a tunneled device advertises certain capabilities to peer devices of a network, and discovers capabilities of peer devices of the network. In a second embodiment, each device of a tunneled network derives a network parameter from a transit protocol parameter for use in data networking.

Methods and apparatus for transporting data through network tunnels

A high-speed I/O interface that allows a number of native I/O formats to be encapsulated into PCIe Vendor Defined Messages ('VDMs') for transfer over a single physical medium, preferably optical, and is thus referred to as the converged I/O ('CIO') interface. The devices can be designed to provide synchronization (time value, frequency, and phase) among a network of routers, with signal paths of several meters, thereby providing an accurate time base suitable for exacting audiovisual applications.

Converged computer I/O system and bridging mechanism for peer-to-peer communication

A high-speed optical interface for connecting computers to external I/O devices allows a number of native I/O formats to be encapsulated into PCIe Vendor Defined Messages ('VDMs') for transfer over a single physical medium, preferably optical, and is thus referred to as the converged I/O ('CIO') interface. Standard PCIe bridges are modified to support peer-to-peer communications, allowing greater exploitation of the capabilities of PCIe.

Bridging mechanism for peer-to-peer communication

The transfer of video and graphic data from a frame buffer to a display system is interleaved in a manner which permits operation with a reduced memory bandwidth. For those scan lines of a display in which the video information appears, video data is retrieved from the frame buffer during the horizontal blanking time of the scan. Graphical data is retrieved from the memory during the active portion of horizontal scan line. By alternating the retrieval of data in this manner, a lower bandwidth operation can be employed, thereby reducing the expenses of the memory. An address translator permits video and graphic data that is stored in different respective formats to be retrieved with a consistent addressing approach. The use of multiple color look-up tables permits full-color video to be displayed even if limited-color graphics are being employed.

Method and apparatus for translation and storage of multiple data formats in a display system

Computer system for displaying video and graphic data with reduced

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Menlo Park, CA, United States of America

Michael W Murphy